Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/64813
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dc.contributor.authorVisamangalam Thattai Lakshminarayanan
dc.date.accessioned2015-06-04T07:04:06Z
dc.date.available2015-06-04T07:04:06Z
dc.date.copyright2014en_US
dc.date.issued2014
dc.identifier.urihttp://hdl.handle.net/10356/64813
dc.description.abstractAs the trend of device integration moves from VLSI to ULSI, number of problems have arisen for 3 dimensional integration of ICs with TSV technology. The increasing complexity and number of components on the substrate is expected to rise faster before Nano-technology takes over. 2.5DICs are a viable market alternative till the 3DIC processes and methods mature. 3DICs require multiple ICs to be placed on top of each other and interconnected by TSVs, which cause power delivery and thermal delivery problems. Individual known good dies connected in 3D fashion gives poor yields and get discarded if the integrated IC fails. 2.5DICs allow interconnection of multiple chips on the same Si substrate placed side to side with interconnections made using Si interposer with multiple metal layers. In this project, non conventional transmission line structures are proposed to improve the layout density of wide 10 high speed data links. The configurations are modelled and characterized using full wave 3D Electromagnetic field simulator. Results are validated based upon eye diagrams and loss parameters. A Current mode driver circuit is designed and simulated using STM 65nm technology node.en_US
dc.format.extent67 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen_US
dc.titleDesign analysis of data links in 2.5DICsen_US
dc.typeThesis
dc.contributor.supervisorKim Tae Hyoungen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Electronics)en_US
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