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|Title:||Design of power management circuits for fully on-ship applications||Authors:||Tan, Xiaoliang||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2015||Source:||Tan, X. (2015). Design of power management circuits for fully on-ship applications. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||With the fast growing electronic portable devices, power management becomes an important area in electronic industry to reduce the power consumption so as to extend the battery life of these devices. Low dropout (LDO) regulator is widely used in power management IC due to its simple structure, low noise and fast speed characteristics. As the technology continues scaling down to deep submicron, the digital circuits display less immunity to Process, Supply voltage, and Temperature (PVT) variations. Therefore, power management technique with PVT compensation becomes another important design approach. This work focuses on the design techniques which include process variation sensing circuit (VTH sensor), wide load capacitance (CL) range with fast speed LDO regulators and digital system supply with PVT compensation capability using LDO regulator.First, the VTH sensor circuit can generate the VTH of a single MOSFET at 0 K (VTH0). VTH0 is temperature and supply invariant but process dependent. The VTH sensor can be utilized to sense the VTH variation of the devices, hence providing the process information. Based on a Brokaw structure with the addition of the proposed current-mode second-order temperature compensation network, this improves the Temperature Coefficient (T.C.), the VTH sensor. Second, a DSMFC technique is proposed in a Flipped Voltage Follower (FVF) LDO regulator architecture. By adding an extra Miller compensation stage, the dominant pole of the feedback system can be pushed to lower frequency whilst the non-dominant pole(s) can be pushed to higher frequency. This extends the CL driving range without sacrificing circuit complexity and quiescent power consumption. Third, a novel Weighted Current Feedback (WCF) technique is proposed in a multi-gain stage LDO regulator architecture. Through feedback of a weighted current, the WCF permits smart management of the output impedance as well as the gain from the inter-gain stage. As a result, a good optimization of stability, speed and accuracy can be achieved in the context of wide CL range. Finally, a PVT Compensated Supply (PVTCS) for driving point-of-load digital system is designed. By adding a weighted combination of the VTH drift of the PMOS (ΔVTHP) and NMOS (ΔVTHN) diodes onto the reference voltage of a high speed WCF LDO regulator, the supply voltage of the digital circuits is adjusted adaptively. This can reduce the speed deviations of the digital circuits under PVT variations. With the low T.C. VTH sensor circuit to sense the process information, the two wide CL range LDO regulators to drive the digital circuits and the PVTCS to compensate the PVT variations of the digital systems, the works are useful for fully on-chip power management circuits with PVT compensation.||URI:||https://hdl.handle.net/10356/64897||DOI:||10.32657/10356/64897||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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