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|Title:||Low power data-driven dynamic logic circuits||Authors:||Zhang, Han||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2014||Abstract:||Dynamic Logic is used in high performance circuit designs for its high speed and less transistor needed to implement a same function compared to Static Logic. Data-Driven Dynamic Logic utilizes input data to replace clock signal as control of pre-charge and evaluation phase. By elimination the clock, less power consumption can be obtained without speed degradation. In this project, Data-Driven Dynamic Logic is undertaken to design CMOS circuits concentrating on power and speed performance. Full Adders are designed with D3L technique and Domino, NP-CMOS circuit techniques to compare the performance trade-offs. 4-bit Ripper Carry Adder, 4-bit Kogge-Stone Adder and 16-bit Kogge-Stone adder are also implemented and simulated using Cadence Virtuoso software. The results show that Data-Driven Dynamic Logic circuits are able to work under low supply voltage. For simple basic logic, D3L logic may save power at the cost of longer pre-charge time. When Data-Driven Driven Dynamic Logic is applied to 16-bit Kogge-Stone Adder, the advantage becomes evident that it is 13% faster and the power consumption is 15% lower.||URI:||http://hdl.handle.net/10356/64960||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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