Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/6512
Title: Package and board level reliability modeling of advanced CSP pakages for telecommunication applications
Authors: Tee, Tong Yan
Keywords: DRNTU::Engineering::Manufacturing::Product engineering
Issue Date: 2005
Source: Tee, T. Y. (2005). Package and board level reliability modeling of advanced CSP pakages for telecommunication applications. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Market for telecommunication products (e.g., mobile phones) is very competitive, demanding products which are more reliable, higher performance, lighter, smaller, cheaper, and shorter time-to-market. These technology requirements are possible with the recent development of advanced Chip Scale Packages (CSPs), such as thin-profile fine-pitch Ball Grid Array (TFBGA), Quad-Flat-No-lead (QFN), and wafer-level CSP (WL-CSP). However, due to limited product development time, these CSPs are usually not tested and studied in detail before introduction to the market. As a result, the package design may not be optimized for various reliability requirements, e.g., popcorn, thermal cycling test, and drop test.
URI: https://hdl.handle.net/10356/6512
DOI: 10.32657/10356/6512
Rights: Nanyang Technological University
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:MAE Theses

Files in This Item:
File Description SizeFormat 
MAE-THESES_955.pdf18.41 MBAdobe PDFThumbnail
View/Open

Page view(s) 10

573
Updated on May 12, 2021

Download(s) 10

370
Updated on May 12, 2021

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.