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|Title:||Low power asynchronous 8051 implementation and evaluation||Authors:||Ne Kyaw Zwa Lwin||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Applications of electronics||Issue Date:||2014||Abstract:||With the increasing demand for low power device in consumer electronics and biomedical field, the requirement and constraint for designing low power chip also increase. Due to the presence of clock network and clock skew, the larger chip area in design, such as microcontroller, presents the increasing difficulty in reliable clock network. Asynchronous design technique offers the alternative to this problem with its absence of a clock signal. Besides, it also provides other benefits in terms of power and robustness in a wide range of power and Process-Voltage-Temperature (PVT) variation. This thesis pertains to the design, implementation and evaluation of a low power asynchronous 8051 microcontroller for low power applications. The low power aspect of the microcontroller is based on the asynchronous methodology and voltage scaling. The asynchronous 8051 microcontroller is implemented using STM 45nm CMOS technology and integrated with ROM, RAM and XRAM blocks. The custom-designed asynchronous SRAM is used for all three memory blocks. The core design is based on the Balsa netlist, a synthesizing language for asynchronous systems. The microcontroller and asynchronous SRAM are tested and evaluated. The SRAM is able to operate down to the lowest voltage of 0.25V. It is also found that SRAM can operate at maximum of 150 MHz and minimum of 79 KHz respectively at nominal 1 V and 0.25V. The asynchronous 8051 microcontroller has 50% and 93% power reduction from nominal voltage when voltage is scaled down to 0.8V and 0.4V respectively. The power efficiency of the microcontroller can also be boosted by 13% through scaling the supply voltage down to 0.8V.||URI:||http://hdl.handle.net/10356/65139||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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