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|Title:||Ultra low power data converters for implantable medical devices||Authors:||Tang, Howard||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2014||Source:||Tang, H. (2014). Ultra low power data converters for implantable medical devices. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||Implantable medical systems like pacemaker and complete intraocular retinal prosthesis offer new hope to one's life in terms of their clinical opportunity. However, for intertwined reasons of size, heating and cost of the system, the energy efficiency of the electronics, including the Analog-to-Digital Converter (ADC), have to be placed with paramount importance. Therefore, this thesis focuses on the analysis, design, and implementation of ultra-low-power ADC for implantable medical systems. The general guideline to design the ADC for implantable medical system is to maintain a moderate sampling speed and resolution with excellent energy efficiency. As a result, Successive-Approximation-Register (SAR); which provides a good compromise among energy efficiency, conversion accuracy and design complexity, is chosen as the main architecture for the development of the ultra-low-power ADC. In this thesis, three different types of SAR ADC are proposed. The first SAR ADC is designed with an Adiabatic Charging Charge Redistribution DAC. Therefore, the dynamic power consumed by the Capacitive DAC can be recovered in an adiabatic manner. The second SAR ADC is implemented in 65nm CMOS process for general purpose implantable medical device. At this process geometry, leakage and parasitic power consumption will become one of the key determinants for overall power consumption. Therefore, this ADC employs the highest degree of simplicity in the architecture to minimize the transistor counts, thus, the source of leakage. In addition, symmetrical layout technique is widely adopted to minimize metal routing; and hence, the parasitic power consumption. This ADC achieves a power consumption of 5.8nW with 9.1-ENOB at 1kS/s. The third SAR ADC is implemented in 180nm CMOS process for implantable retinal prosthesis. At this process geometry, leakage and parasitic power consumption is of less prominent and dynamic power consumption dominates the overall power efficiency. Therefore, this ADC adopted a Supply Reduction Technique which slashes the supply voltage required for a given input range by half and result in an instant reduction of 75% in overall power consumption. This ADC achieves a power consumption of 1.33µW with 8.02-ENOB at 100kS/s.||URI:||http://hdl.handle.net/10356/65203||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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