Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/65234
Title: Memory- and energy-efficient VLSI architectures for 2-D discrete wavelet transformation
Authors: Hu, Yusong
Keywords: DRNTU::Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision
Issue Date: 2015
Source: Hu, Y. (2015). Memory- and energy-efficient VLSI architectures for 2-D discrete wavelet transformation. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: DWT has been applied to various applications such as image analysis, video processing and computer graphics. The conventional general purpose processors are unable to satisfy the hunger for computational speed and the demand for energy efficiency at the same time. Therefore, specifically designed VLSI DWT architectures are required to tackle the issue. In this thesis, the architecture for 2-D DWT is studied and novel 2-D DWT architectures are proposed which achieve high memory and energy efficiency. Broadly, the research is motivated by improving two most important performance metrics, namely silicon area and energy efficiency. The thesis details the development of the proposed data scanning methods, the computation scheduling, the evaluation of energy efficiency, the proposed hardware architectures, the performance evaluation of the architectures and the comparison with the state-of-the-art designs.
URI: https://hdl.handle.net/10356/65234
DOI: 10.32657/10356/65234
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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