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|Title:||Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems||Authors:||Zhou, Rong||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2015||Source:||Zhou, R. (2015). Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||In the past decades of electronic circuit designs, the synchronous-logic (sync) is the main de-facto design approach for digital systems. This is largely due to its synchronization to a global clock signal (or its variants thereof) which simplifies the data transfer. Nevertheless, designing digital circuits and systems based on sync approach is becoming more challenging due to the increase in process, voltage and temperature (PVT) variations in the deep submicron fabrication process. An alternative design approach which is based on the asynchronous-logic (async), is potentially more robust against the PVT variations, lower power dissipation and higher speed due to the absence of the global clock signal. In async design approach, the Quasi-Delay-Insensitive (QDI) circuit is probably the most practical and robust design methodology. This thesis pertains to the investigation of high robustness, low design effort and low overhead async QDI digital design. Three contributions have been made in this thesis as follows. First, a synthesis tool for designing the async QDI systems based on sync specifications is proposed. The proposed synthesis tool has the following salient features. The coding specifications are constructed based on the standard Verilog HDL language, to seamlessly integrate into the standard synchronous circuit design flow, giving it full leverages to design async QDI circuits by using the commercial Electronic Design Automation tools. The targeted synthesized async QDI circuits are robust against the PVT variations. To verify the effectiveness of the proposed synthesis tool, an 8-bit 8-tap async QDI Finite Impulse Response (FIR) filter based on IBM 130nm CMOS process is synthesized and implemented; it dissipates 3.7mW @ 5MHz sampling rate and features 0.74nJ per operation, whereas the reported async design methodology dissipates 1.13nJ per operation (1.53× energy per operation as that of the proposed methodology). Second, a novel microcell-interleaving approach is proposed to reduce the overhead of async QDI data path synthesized by the proposed synthesis tool. The performance of the async QDI data path designed by the microcell-interleaving approach is evaluated in terms of power dissipation, transistor-count, circuit delay and the upper / lower boundaries of these performance profiles. A Microcell-Interleaving Genetic Algorithm (MIGA) is further proposed and implemented to stochastically optimize the power dissipation, transistor-count, and delay of the benchmarking circuits based on the proposed microcell-interleaving approach. The async QDI circuits optimized by the MIGA, on average, dissipate 349µW @50MHz, feature 6917 transistors. Comparatively, the reported async QDI methodologies dissipate 617µW@50MHz (1.77× power dissipation as that of the proposed methodology), feature 9684 transistors (1.4× transistor count as that of the proposed methodology). Third, a pipeline-granular async QDI dynamic voltage scaling (DVS) technique with low overhead is proposed to maintain minimum power dissipation of async QDI pipelines to perform necessary operations while accommodating the PVT variations. In the proposed async QDI DVS technique, the completion of the circuit operations is automatically detected by completion detection (CD) circuits, without additional timing margin assumption. The power supply unit (PSU) is integrated on-chip with three voltage scales, 0.5V for low-speed operations, 0.8V for medium-speed operations and 1.2V for high-speed operations. The PSU adaptively adjusts the supply voltage of each pipeline stage according to their corresponding work-loads, thereby maintaining minimum power dissipation. To validate the proposed async QDI DVS technique, an async QDI FIR filter is implemented. The results show that the async QDI multiplier pipeline stage with the proposed async QDI DVS technique features a low power dissipation of 89.9µW@50MHz, whereas the async QDI multiplier pipeline stage with the conventional design methodology dissipates 613.1µW@50MHz (6.82× power dissipation as that of the proposed methodology). In summary, this thesis has proposed a synthesis tool, a microcell-interleaving optimization, and a DVS technique for low overhead and robust async QDI circuits with low design effort.||URI:||https://hdl.handle.net/10356/65411||DOI:||10.32657/10356/65411||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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Updated on May 10, 2021
Updated on May 10, 2021
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