Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/65480
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dc.contributor.authorLiu, Lifenen
dc.date.accessioned2015-10-06T03:18:57Zen
dc.date.available2015-10-06T03:18:57Zen
dc.date.copyright2015en
dc.date.issued2015en
dc.identifier.citationLiu, L. (2015). Low-power column-parallel ADC for CMOS image sensor by leveraging spatial likelihood in natural scene. Master's thesis, Nanyang Technological University, Singapore.en
dc.identifier.urihttps://hdl.handle.net/10356/65480en
dc.description.abstractColumn-Parallel analog-to-digital converter (ADC) technology has often been integrated in CMOS Image Sensors as a system-on-chip (SoC) solution, in particular for portable devices. Since the power consumption of column-parallel ADCs in CMOS image sensors play an important role in total power consumption, a low-power application on has been developed specifically for integration in low-power image systems. In a conventional column-parallel ADC design, the ADC operation is repeated row to row, column to column and frame to frame, regardless of the properties of the scenes. In this thesis, a new operating method is proposed, which takes into account spatial likelihood in natural scenes. In the proposed method, the MSBs of selected pixel would be predicted before the ADC operation, based on that pixel’s neighbor pixels in the previous row. Because there is strong correlation between consecutive rows in most natural scenes, pre-ADC pixel estimation could save bits in ADC conversion cycles. The total number of ADC conversions would effectively be reduced, resulting in lower power consumption. This method was verified in extensive Matlab simulations, where ADC conversion cycles were reduced by up to 20%-30% for most natural scenes and a saving of up to 29.49% was achieved in switching energy for a 512×512 resolution Lena image. This thesis presents the design of a column-parallel low-power ADC system for a CMOS image sensor with the proposed algorithm. The system was implemented in AMS 0.35 μm CMOS technology. The study also details the simulation of the algorithm and the testing of the hardware. Improvements made to the algorithm after the analysis and testing of the CMOS imaging sensor are described at the end of the thesis.en
dc.format.extent126 p.en
dc.language.isoenen
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleLow-power column-parallel ADC for CMOS image sensor by leveraging spatial likelihood in natural sceneen
dc.typeThesisen
dc.contributor.supervisorChen Shoushunen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.description.degreeMASTER OF ENGINEERING (EEE)en
dc.contributor.researchCentre for Integrated Circuits and Systemsen
dc.identifier.doi10.32657/10356/65480en
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