2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip

Abstract

In the past few decades, the design of computers has been primarily driven by improving performance with faster clock frequency of single-core processor using transistor scaling. The transistor scaling towards high performance of fast clock frequency is, however, stuck recently due to the constraint of power density (or thermal reliability). By exploiting parallelism, multi-core processor based design of computers has emerged to scale up performance of throughput under power budget. As such, the scaling paradigm has changed to integrate as many processor cores as possible on one single chip. In the traditional 2D based memory-logic integration, the scalability of many-core integration is limited by the communication between the cores and memory to access via I/O interconnections, which pose stringent requirements for high utilization efficiency of both bandwidth and power.In order to explore the fundamental challenges of I/O interconnections by 3D TSVs and 2.5D TSIs for many-core integration, in this thesis, we have studied various design aspects starting from device level modeling to system level management with the works done on modeling, circuit design, system design with power and bandwidth management as the main focus.