Design of a full CMOS voltage reference

Abstract

In integrated circuits, voltage reference is an essential part to provide precise and stable voltage as a supply for other sub-blocks in entire circuit. Compared with simple established resistor divider, the voltage reference has inherent constant voltage output which is independent of variation in supply voltage, load resistance, load current, temperature, or aging over time. In this project, the current mode approach with full CMOS band-gap voltage reference is designed using CSM 0.18 μm process and simulated in Cadence tool. Design of CMOS transistors in sub-threshold region allows this 720.294 mV typical voltage reference to operate with temperature coefficient of 35.3788 ppm/°C for the temperature range from -20°C to 80°C under 1-Volts power supply. Power supply rejection ratio (PSRR) is -28.6635 dB at 100Hz. The total current consumption is 746.12 nA. The circuit is extremely stable with 88.7398° phase margin and 41.0375 dB gain margin.