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|Title:||Analysis and design of a highly efficient and versatile DC-DC converter||Authors:||Yu, Guolei||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2015||Source:||Yu, G. (2015). Analysis and design of a highly efficient and versatile DC-DC converter. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||The thrive of battery-operated devices and connected devices with the vision of Internet-of-Things (IOT) calls for efficient and versatile Direct Current to Direct Current (DC-DC) converters to fulfil the ever-growing power demand. Adaptive on-time (AOT) control of DC-DC converters has the advantages of simple structure, good light load efficiency and fast response to load step. The purpose of this research is to develop AOT control in two areas: digital control for its process scalability and flexibility, and ultra-low-power operation. Novel circuit blocks and techniques have been developed to improve the performance of AOT control, which are listed as follows. For data conversion required by digital control, a flash analog-to-digital converter (ADC) using NOR gates as comparators has been proposed and verified by simulation and a prototype chip using 0.35 µm CMOS process. The advantages of the proposed ADC include low power, high speed and small silicon area. Two methods have been proposed to achieve near optimum load transient response: level-based multi-loop control and body-brake. Level-based multi-loop control is able to achieve near minimum output voltage deviation during load transient using a simple algorithm. A new detection method is proposed for body-brake technique to further improve the unloading response. A counter-based dead-time optimization method has been proposed to improve conversion efficiency under heavy load. Under specific simulation conditions, 2.3% efficiency improvement has been observed. In the study of ultra-low-power operation, we further develop the existing method of duty-cycled operation that dynamically changes the system operation frequency with a low-power relaxation oscillator. The duty-cycled operation is referring to the scheme that all active circuit blocks except the system clock are turned off when all the outputs are in regulation, hence the system quiescent current reduces to the system clock block current only. It has also demonstrated that making on-time adaptive to input voltage improves the peak efficiency by about 1% over the input range of 2.65 V to 3.3 V, by a prototype chip using CMOS 0.18 µm process.||URI:||https://hdl.handle.net/10356/65841||DOI:||10.32657/10356/65841||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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