Novel techniques for RF and millimeter-wave frequency generation circuits in CMOS technology
Date of Issue2016
School of Electrical and Electronic Engineering
Centre for Integrated Circuits and Systems
The rapid advancement of RF and millimeter-wave communication systems has imposed stringent requirements on frequency generation circuit. As phase-locked-loop (PLL) features frequency synthesis as well as the capability of calibrating frequency shift caused by temperature and voltage variation, it is usually regarded as the best candidate for frequency generation. In a typical PLL, voltage-controlled oscillator (VCO) and frequency divider (FD) are building blocks of utmost importance. For VCO, trade-offs exist among phase noise, tuning range and power consumption, while for FD, trade-offs are among locking range, division ratio, highest operating frequency and power consumption. In this thesis, four novel circuits and design techniques are proposed to address the issues and challenges associated with high-frequency VCO and FD across three distinct bands of 5 GHz, 24 GHz and 60 GHz. These bands are all unlicensed Industrial-Scientific-Medical (ISM) bands, where 5 GHz and 60 GHz are regulated by IEEE 802.11ac and 802.11ad standards for high-data-rate communication, and 24 GHz is utilized to implement point-to-point backhaul communication. With the invention of these novel circuits, some technical issues in frequency generator for mainstream communication application are solved. Firstly, a low-power low-phase-noise VCO with self-adjusted active resistor (SAAR) is presented. A pair of PMOS transistors is introduced between NMOS cross-coupled pairs and LC-tank, serving as the SAAR. When the cross-coupled transistor resides in the saturation region, SAAR exhibits small resistance, enabling fast switching and suppressing flicker noise up-conversion to 1/f3 phase noise. Moreover, as cross-coupled transistor enters triode region, SAAR will adjust to larger resistance and prevent the small conducting resistance of the cross-coupled transistor degrading the quality factor of LC tank. Fabricated in a 65 nm CMOS technology, the proposed VCO demonstrates a tuning range of 5.07-6.35 GHz (22.4%) with only 0.42 mW power consumption at 0.6 V supply. The phase noise under worst case scenario is -40.8 dBc/Hz at 1 kHz and -111 dBc/Hz at 1 MHz. Compared with state-of-the-art VCOs working at similar frequency, this work achieves superior FoM (1/f3). Meanwhile, 1/f2 phase noise is not compromised, with best FoM (1/f2) and FoMT accomplished among these works. Secondly, a K-band differential VCO was developed, which aims to solve the potential problems of start-up and limited oscillation frequency, in a low-cost less-advanced technology. A hybrid technique that combines open-loop digitally-controlled tail current with switchable auxiliary cross-coupled pairs (ACCPs) is proposed to ensure robust start-up for wideband operation. Compared with prior close-loop current controlling method, the proposed technique does not suffer from phase noise degradation. Furthermore, by evenly distributing the ACCPs, transistors with smaller size are allowed to achieve the same start-up condition, which leads to frequency boost and phase noise improvement. Implemented in 0.18 μm CMOS technology, the VCO achieves a wide frequency tuning range of 21.38 - 26.34 GHz (21%) and a low phase noise of -106 dBc/Hz at 1 MHz offset from 26.3 GHz carrier frequency. At 1.1 V power supply, the power consumption of the core circuit is 7.9 - 11.4 mW across the entire output frequency range. Among reported K-band VCOs in sub-micron technologies, this work accomplishes the highest FoMT as well as the highest FoMT/V which evaluates the tuning capability in terms of the tuning voltage range. Thirdly, by using the novel frequency-dependent injection enhancement (FDIE) technique, a V-band divide-by-three injection-locked frequency divider (ILFD) with low power consumption and wide locking range is presented. The FDIE circuit is analyzed for optimum trade-off between amplitude and phase locking conditions to obtain the greatest locking range. Then, the method of employing a current-reused differential pre-amplifier loaded with a moderate-k transformer for FDIE circuit is proposed and proven theoretically. Fabricated in a 65 nm CMOS technology, the ILFD prototype demonstrates a wide input locking range of 54.5-62.36 GHz (13.5%) and only 2.5 mA current consumption with 1.2 V supply. Compared with state-of-the-art V-band divide-by-three ILFDs, this work features the best FoM. Finally, a 60 GHz CMOS regenerative frequency divider (RFD) with large divisors of 27/28/29/30 which can enable a 60 GHz cascaded PLL architecture to achieve significant suppression of VCO phase noise is demonstrated. The four divide modes are realized by changing the status of the feedback I/Q signals, which are applied to the single-sideband mixer at the first stage. Designed in 65 nm CMOS technology, the RFD leads to a compact layout with a core size of 0.4mm × 0.3mm. With 0dBm input power and without any frequency tuning mechanism, post-layout simulation results reveal that the FD achieves locking range larger than 11% for all divide modes. The overall power consumption of the RFD is 16 mW at 1.2/0.6 V power supply. This design demonstrates the first 60 GHz frequency divider with variable division ratios larger than 20.
DRNTU::Engineering::Electrical and electronic engineering