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|Title:||Design of high speed high resolution ADC with innovative architecture and circuits||Authors:||Qiu, Lei||Keywords:||DRNTU::Engineering::Computer science and engineering::Hardware::Integrated circuits||Issue Date:||2016||Source:||Qiu, L. (2016). Design of high speed high resolution ADC with innovative architecture and circuits. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||Nowadays, the demand for high performance Analog-to-Digital Converter (ADC) is growing rapidly. The high-speed high-resolution ADCs play important role in many systems, such as wireless base station, software-defined-radio (SDR), test system, etc. Due to the development of process technology, low power and high performance ADC design becomes more attractive. Therefore, there is continuous interest in designing the high-speed high-resolution and low power ADCs. The mismatches between channels in multi-channel architecture degrade the linearity of overall ADC systems. In this research work, the mismatches calibration for two kinds of multi-channel ADCs, time-interleaved ADCs (TI-ADCs) and frequency-interleaved ADCs (FI-ADCs), are proposed. The time skew estimation technique adopts the correlation between channels, which indicates the value of time skew. And the time skew correction techniques are divided into two categories: analog trimming and digital compensation. In addition, the analysis of frequency-interleaved ADCs is addressed. An efficient calibration method for frequency-interleaved ADCs is proposed to compensate the analog analysis filter mismatches and gain mismatches, which could promote the FI-ADCs as a competitive multi-channel ADC alternative to TI-ADCs. It is known that SAR ADCs are more energy efficient than pipeline ADCs. However, the typical structure of SAR ADC is difficult to operate at high speed (>250MHz). To increase the sampling rate of single channel SAR ADC. A 10-bit 300MS/s SAR ADC with interpolated 2b/cycle architecture is proposed. By using the asynchronous timing, less time is needed for the conversion cycles. In addition, the conventional shift register based successive approximation algorithm has been optimized, which reduces the settling time for the DAC array. A background offset calibration technique is presented to eliminate of effect of the offsets between comparators. The ADC chip was fabricated in a 40nm CMOS low power technology. The measurement results show that the ADC achieves a SNDR of 51.5dB and with a figure of merit (FoM) of 58fJ/conversion-step when operating at 300MS/s and 147MHz Nyquist input. The ADC core achieves a small area of 0.032mm2. Time-interleaving is a popular approach to extend ADC speed. A 10-bit 1GS/s 4-way time-interleaved (TI) SAR ADC is presented. Each channel exploits a 250MS/s SAR ADC with high speed non-binary searching approximation that allows the conversion to obtain settling error tolerance. The non-binary DAC associated with adders based encoding circuit are custom designed, which eliminates multiplier based encoding logic and thus, simplifies the digital circuitry and reduces the digital power. To suppress the time skew among the TI SAR ADC, the sampling instant of the sub-ADC channels are synchronized to the full rate master clock, which reduces the time skew spurs below -52 dB at Nyquist input. Moreover, a digital background low computational time skew calibration technique with interpolation FIR filters is proposed, which further suppresses the timing mismatch spurs to be less than -70dB. The prototype was fabricated in a 65nm CMOS technology. The measurement results show that the ADC achieves a SNDR of 49.6dB and with a figure of merit (FoM) of 37fJ/conversion-step when operating at 1GS/s and 458.1MHz Nyquist input. The ADC core achieves a small area of 0.03mm2.||URI:||https://hdl.handle.net/10356/67024||DOI:||10.32657/10356/67024||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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Updated on Jun 21, 2021
Updated on Jun 21, 2021
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