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|Title:||Low power smart sensor circuits for biomedical applications : applications to neural interfaces||Authors:||Yao, Enyi||Keywords:||DRNTU::Engineering||Issue Date:||2016||Source:||Yao, E. (2016). Low power smart sensor circuits for biomedical applications : applications to neural interfaces. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||In this thesis, we proposed a novel low power, compact, current-mode spike detector with feature extractor for real-time neural recording systems where neural spikes or action potentials (AP) are of interest. Such a circuit can enable massive compression of data facilitating wireless transmission. This design can generate a high signal-to-noise ratio (SNR) output by approximating the popularly used nonlinear energy operator (NEO) through standard analog blocks. We show that a low pass filter after the NEO can be used for two functions – (i) estimate and cancel low frequency interference and (ii) estimate threshold for spike detection. The circuit is implemented in a 65 nm CMOS process and occupies 200 μm x 150 μm of chip area. Operating from a 0.7 V power supply, it consumes about 30 nW of static power and 7 nW of dynamic power for 100 Hz input spike rate making it the lowest power consuming spike detector reported so far. The feature extractor could be utilized to extract some features from the raw waveform that have enough information to discriminate between different shapes of recorded spike waveforms. The spike sorting was performed by our proposed hardware extreme learning machine system (ELM) which is a low power neuromorphic machine learner that can perform the local processing in smart sensors while dissipating very low power. The proposed circuit utilizes device mismatch prevalent in today's VLSI process to perform a significant part of the computation while a digital back end enables precision in the final output. The particular machine learning algorithm we use is extreme learning machine (ELM). Mismatch in silicon spiking neurons and synapses are used to perform the vector-matrix multiplication that forms the first stage of this classifier and is the most computationally intensive. System simulations and measurement have been conducted to evaluate the dependence of performance (in a classification and a regression task) on analog and digital parameters like weight resolution, maximum spike frequency etc. It is shown that the proposed implementation is more energy efficient as opposed to custom digital implementations for a classification task. In order to verify its function, some real-world bench mark binary classification datesets have been employed in the measurement showing that the performance of our design is comparable with recent publications and software simulations of other machine learning system. This system was implemented in a 0.35 μm CMOS process which can operate from 0.8 V to 3.3 V power supply with a lowest classification energy 0.2 nJ/op, maximum classification speed 564 MMAC/s.||URI:||http://hdl.handle.net/10356/67221||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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