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|Title:||Development of 3D electro-optical integration based on silicon photonic TSV interposer||Authors:||Yang, Yan||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2016||Source:||Yang, Y. (2016). Development of 3D electro-optical integration based on silicon photonic TSV interposer. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||Silicon photonics has been intensively researched and investigated as it provides a low-cost and power efficient solution for next generation interconnect technology based on on-chip, chip-to-chip, and long-haul optical communication. A multifunctional platform requires photonic integrated circuits (PICs) and complementary-metal-oxide-semiconductor (CMOS) circuits to be integrated in the same system. To achieve advantages of power efficiency and bandwidth densities of PIC, monolithic integration of CMOS circuits and silicon photonic functional blocks has been explored recently. However, this approach has some limitations, such as increased number of mask layers, sophisticated co-integration processing skills on the same silicon chip, huge size mismatch between CMOS and photonic functional blocks, and therefore resulted in low overall yield. In this work, the separate fabrications of silicon photonic devices and CMOS circuits are designed and experimentally demonstrated, and their integration is achieved using through-silicon-via (TSV) and flip-chip bonding technology, which is a three-dimensional (3D) integration scheme. With the scenario of interconnection along vertical dimension, the 3D integration scheme provides a shorter communication routing and lower power dissipation, and therefore has becoming one promising solution for continued scaling of tera-scale communication systems. In this thesis, the technology options/integration strategies of electro-photonic integration based on silicon-on-insulator (SOI) photonic interposer featuring TSVs and flip-chip bonding technology are proposed and investigated. An SOI photonic TSV interposer for the purpose of inter/intra-chip optical/electrical communication interface routing is proposed, in which TSVs are fabricated in an SOI photonics wafer. In this 3D integration scheme, high density metal lines and micro-bumps in the flip-chip bonding technology provide interconnection among guest dies, and TSVs communicate with I/O ports on the organic package (e.g., fc-BGA) and/or printing circuit board (PCB), whereas silicon photonic devices deal with huge amount of data transmitted in from and out to the external world. TSV is a key technology in the 3D integration, which provides flexible and compact electrical/physical connectivity between different chips. The first investigation in this thesis is the TSV-induced impact on the optical performance of photonic devices. To realize compact scaling, which is one of the important benefits of 3D integration, high-density TSVs are situated close to the silicon photonic devices in the photonic interposer. One of the critical limitations in the compact 3D photonics integration is the TSV-induced stress, which affects the performance of silicon photonic devices integrated in interposer, particularly for the stress-sensitive devices, such as silicon photonic ring resonators. The impact of TSV-induced stress is analyzed, and the model of TSV-induced stress distribution in the silicon waveguide in SOI photonic interposer is built. The model of the change in effective-refractive-index caused by stress-induced changes of refractive index tensors is presented. Silicon photonic double-cascaded ring resonators integrated with TSV structures on an SOI platform are fabricated and characterized to demonstrate the impact of TSV-induced stress. The characterization results are statistically analyzed with the impact of fabrication non-uniformity eliminated. Finally, a stress aware design framework and a TSV keep-out-zone (KOZ) for the silicon photonic ring resonator are proposed. A compact scaling of SOI photonics interposer is ultimately achieved. The second part of design and fabrication in this thesis is a silicon photonic interposer with monolithically integrated active/passive photonic devices featuring Cu-based back-end-of-line (BEOL), including Mach-Zehnder Interferometer (MZI) optical modulators, photodetectors (PD) and thermo-optically (TO) tunable arrayed waveguide gratings (AWG). From the integration and packaging perspective, CMOS-compatible Si photonics technology is becoming one of the most promising technologies to realize very large-scale complex photonics-CMOS integration system. To take advantages of the CMOS semiconductor technology, such as high integration density, low-cost and good reliability, the progress of silicon photonics technology should further maintain standardization and adherence to the established CMOS technology methodologies. CMOS semiconductor industry has been progressing from Al-based BEOL interconnects to Cu-based at technology nodes beyond 0.18 µm. Due to Cu’s higher conductivity and lower skin-effects, Cu-BEOL is also expected to enable better RF performance and higher I/O density in silicon PICs and active devices. Furthermore, Cu-BEOL based Si-photonics provides the toolboxes for the Si photonics-CMOS integration strategy based on Si photonics interposer featuring TSVs and flip-chip bonding technology. As important active devices, MZI modulators and Ge PDs monolithically integrated in this interposer featuring radio-frequency (RF) traveling-wave electrode (TWE) via Cu-BEOL is explored with a higher speed. A latticed Cu surface pattern is designed for the Cu-BEOL. The modulator is designed with Cu-TWE for better RF performance and doping compensation for reducing the optical transmission loss of the phase shifter caused by ion implantation. Discrete contact plugs to Ge PD are designed for reducing Cu-induced optical loss and thus improving the responsivity. The 3-dB bandwidths for both stand-alone modulators and PDs on the integrated wafer are 37 GHz and 33.7 GHz, respectively. A transmission data rate of 30 Gbps of the interposer is achieved, which is limited by the measurement setup. It is demonstrated that Cu-TWE with low resistance provides better RF performance with higher bandwidth than Al-based active devices. Cu application can further improve the integration of silicon photonic devices and CMOS circuits in the future. The Cu-BEOL based RF silicon photonic devices toolbox for high performance photonics-CMOS integration has been established. As the key passive photonic device, AWG multiplexer/demultiplexer (MUX/DeMUX) integrated in this interposer is investigated in this thesis. The increasing demand for bandwidth in optical communications has increased the interest for dense-wavelength-division-multiplexing (DWDM) technology. This demand requires high performance wavelength MUX/DeMUX with more channels and small channel spacing. At the same time, one major issue in using a high-index contrast platform such as SOI wafer for photonic devices is its sensitivity to dimensional variations. Dimensional deviations of the devices will cause a wavelength shift in the spectral response. AWGs are larger in size and thus more vulnerable to different sources of dimensional variations, such as the variation in the silicon layer thickness, process non-uniformity, and mask error. Therefore methods for stabilizing and tuning, such as precise positioning of AWGs wavelength, or compensation for optical wavelength drift, are of great interest. By taking advantage of the thermo-optic (TO) effect in Si, thermal tuning method can be utilized. A tunable silicon AWG based on TO effect has been demonstrated for the first time in this thesis. The thermal performance simulation shows that a uniform heating is achieved by the heater design, while the experiment results show that above 600 GHz channel tunability is achieved. Finally, an SOI photonic TSV interposer is designed, modeled and fabricated, in which TSVs, nano-tip waveguide coupler, TO tunable silicon AWG, MZI modulator and Ge PD are monolithically integrated featuring Cu-BEOL. A 3D electro-photonic TSV integration module, including this photonic TSV interposer and electronic chip using TSVs and flip-chip bonding technology, are modeled and experimentally demonstrated and characterized. Cu transmission lines are fabricated on the electronic chip using Cu-RDL process. The fabrication process of the 3D electro-photonic TSV integration including the 100 µm-thick photonic TSV interposer and the elecronic chip using TSVs and the flip-chip bonding technology is proposed and developed. The characterization results show that 40 Gbps-data rate is achieved for the high speed photonic device, and 800 GHz channel tunability is achieved for the TO tunable silicon AWG in the 3D electro-photonic TSV integration. From modeling and experimental demonstration, this 3D electro-photonic TSV integration module provides the toolboxes for the 3D Si photonics-CMOS TSV integration strategy based on Si photonics interposer featuring TSVs and flip-chip bonding technology.||URI:||https://hdl.handle.net/10356/67281||DOI:||10.32657/10356/67281||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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Updated on Aug 2, 2021
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