Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/67530
Title: Image processing on FPGA
Authors: Han, Xinyu
Keywords: DRNTU::Engineering
Issue Date: 2016
Abstract: Reconfigurable hardware like field programmable gate arrays (FPGA) has been proposed as a way of obtaining high performance for computationally intensive DSP applications such as image processing, even under real time requirements. This project firstly explores data transfer between PC and FPGA devices, then the application for image processing features was designed and developed. FPGA is an integrated circuit which contains many programmable logic blocks that allow complex digital logic functions to be performed, which are commonly used in DSP including image processing. This report details the project to develop a communication link between a PC and an FPGA board and leveraged user-friendly interface on PC to facilitate the data transfer. In this way, the whole process of image processing became more convenient and faster. In this project, the hardware module for the FPGA board was designed in Verilog HDL, which was synthesized in the Xilinx ISE Design Suite. The computer application was developed using the Microsoft Visual Studio (C++ / C#) and the Opal Kelly FrontPanel. The connection linked a high-speed USB port on the PC to Xilinx Spartan-6 FPGA board, which allowed image file to be transferred efficiently and conveniently in both directions. As a result, it facilitated the storing and viewing of images on the PC and complex image processing on the FPGA board. This report describes the design and development of the data transfer and image processing via the link between a PC and an FPGA board. Recommendations of future work were also given at the end of the report.
URI: http://hdl.handle.net/10356/67530
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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