Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/67985
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dc.contributor.authorLiauw, Javier Wei Sheng-
dc.date.accessioned2016-05-24T01:00:18Z-
dc.date.available2016-05-24T01:00:18Z-
dc.date.issued2016-
dc.identifier.urihttp://hdl.handle.net/10356/67985-
dc.description.abstractMulti-core System-on-Chips (SoCs) are a promising research area due to their improved speed (due to parallel processing) and possible higher energy-efficiency. Designing an SoC, realized by Network-on-Chip (NoC) is a promising research area applicable to many applications. The basic premises for NoC-based SoCs include good scalability/routability (due to duplication of microprocessor and NoC), improved speed (due to parallel processing) and high energy-efficiency (due to effective routing and computations). The objective of this project is to improve and optimise the existing multi-core 8051 microcontroller with NoCs to achieve better performance in terms of power and silicon area. The tools used are Cadence SoC Encounter, Synopsys Design Compiler and Synopsys VCS simulation tool. The programming languages used include Verilog and Perl and Tool Command Language (Tcl).en_US
dc.format.extent53 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University-
dc.subjectDRNTU::Engineeringen_US
dc.titleFloorplanning, power & area optimization for network-on-chipen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorGwee Bah Hweeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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