Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/67985
Title: Floorplanning, power & area optimization for network-on-chip
Authors: Liauw, Javier Wei Sheng
Keywords: DRNTU::Engineering
Issue Date: 2016
Abstract: Multi-core System-on-Chips (SoCs) are a promising research area due to their improved speed (due to parallel processing) and possible higher energy-efficiency. Designing an SoC, realized by Network-on-Chip (NoC) is a promising research area applicable to many applications. The basic premises for NoC-based SoCs include good scalability/routability (due to duplication of microprocessor and NoC), improved speed (due to parallel processing) and high energy-efficiency (due to effective routing and computations). The objective of this project is to improve and optimise the existing multi-core 8051 microcontroller with NoCs to achieve better performance in terms of power and silicon area. The tools used are Cadence SoC Encounter, Synopsys Design Compiler and Synopsys VCS simulation tool. The programming languages used include Verilog and Perl and Tool Command Language (Tcl).
URI: http://hdl.handle.net/10356/67985
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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