Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/68063
Title: A PSRR-aware CMOS power amplifier for portable applications
Authors: Li, Yao
Keywords: DRNTU::Engineering
Issue Date: 2016
Abstract: Power supply rejection ratio (PSRR) is a crucial factor for audio amplifiers to ensure sound quality in portable devices. Improving PSRR becomes more challenging as power consumption and size of integrated chips (ICs) keep scaling down. In mobile phones, a Time Division Multiple Access (TDMA) noise of 217Hz is fed to the supply rails and creates a “buzz” sound. In order to attenuate 217Hz and hearing range (20-20kHz) supply noise, a high-PSRR, low-power and small-area power amplifier is required. In this project, a basic three-stage class AB amplifier to drive a 16Ω speaker load is used as the benchmark, which has a PSRR of 83.9dB at 217Hz and 44.5 dB at 20kHz. The proposed PSRR improvement is based on adding the LDO. he simulation results shows that the PSRR can be improved to 112.6dB at 217Hz and 73.9 dB at 20kHz. High frequency PSRR is further improved by the proposed LDO with increased output accuracy. The final PSRR achieved in this project is 124.1dB at 217Hz and 98.5dB at 20kHz with about 40dB improvement. The PSRR at low and medium frequency range has been analyzed in detail, whereas the performance at high frequency is discussed. Suggestions are made to resolve the drawbacks of the proposed LDO, like poor transient response and output swing reduction.
URI: http://hdl.handle.net/10356/68063
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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