Multilevel diode clamped converter with space vector modulation and DC-link capacitor voltage balancing
Harikrishna Raj, Pinkymol
Date of Issue2016
School of Electrical and Electronic Engineering
Multilevel converters are very popular in medium/high power conversions due to their capability to generate high quality voltage magnitudes with low harmonics while employing devices of smaller voltage ratings. The output voltage waveform of multilevel inverter consists of multiple steppes of smaller magnitudes designed to reduce electromagnetic interference (EMI) commonly produced by rapid switching that generate lesser common mode currents at motor shaft and bearings due to reduced dv dt . The neutral point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) converters are considered as the three classical multilevel converter topologies which have found their way to industrial applications almost two decades ago. To expand the application field of multilevel converters by overcoming the challenges associated with classical topologies, new multilevel topologies and modulation techniques are developed. In this thesis, various NPC multilevel inverter topologies and its modulation techniques are investigated. Diode-clamped multilevel inverter (DCMI) for more than three-level operation is less attractive due to dc-link capacitor voltage unbalancing issues and increased conduction loses caused by the commutation of (n-1) × (n-2) clamping diodes connected in series per-leg of an n-level diode clamped inverter. A converter topology with minimum number of series connected devices which balance the total voltage equally between the semiconductors and new multilevel modulation schemes, which on more number of levels, redundant voltage vectors and zero common mode voltage vectors available in higher level DCMI, can be used together to solve the above mentioned issues. In this thesis, the voltage unbalance issues and capacitor voltage balancing techniques in DCMI are studied in detail. An extensive analysis of two modulation techniques, level-shifted PWM (LS-PWM) and space vector modulation (SVM) are presented and a SVM based voltage balancing strategy for three-level and five-level diode clamped inverters are developed by utilizing redundant switching vectors without the need of any additional controls or auxiliary circuits. The proposed balancing strategy is tested on a five-level reduced device topology. Multiple-pole multilevel diode clamped inverter (M2DCI) which is derived from three-level DCMI topology and uses lesser number of clamping diodes compared to the classic five-level DCMI. The capacitor currents as well as dc-link intermediate branch currents are obtained from the switching function model of five-level M2DCI, which reduces the number of calculations at each sampling periods while implementing the voltage balancing strategy when compared to sector based methods. The stability limits of the proposed voltage balancing strategy for M2DCI based on load power factor angle and modulation indices have been obtained at various load conditions. The investigations shown here are modeled in Matlab/Simulink® and PSIM environment and verified using experimental results. It is found that to achieve capacitor voltage balancing, modulation index is restricted to about 60% of its maximum value when loads of high power factor i.e PF ≥ 0.8 is connected at the converter terminals. Hence the proposed reduced device topology with SVM technique, which self-balances the dc-link capacitors has been extended for reactive power control in a grid connected environment. Additionally, the application of five-level multiple-pole multilevel diode-clamped converter (M2DCC) as STATic synchronous COMpensator (STATCOM) is investigated with the proposed space vector modulation based balancing strategy. The proposed scheme maintains a balanced voltage across the dc-link capacitors and exchange reactive power at various load conditions. Further, the performance of STATCOM and controllers are investigated through modelling done in Matlab/Simulink® and PSIM environment. The proposed reduced device topology together with SVM based voltage balancing technique is expected to give good performance for reactive power applications by reducing the converter losses, size, weight and THD.
DRNTU::Engineering::Electrical and electronic engineering