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|Title:||ADC architectures for low power analog machine learning||Authors:||David Bose, Christin||Keywords:||DRNTU::Engineering||Issue Date:||2016||Abstract:||With the advent of the concept of Internet of Things (IoT) that aims to wirelessly connect “all” devices, there is a growing need for low-power machine learning systems that can refine the data at the source and transmit only the refined information. Such a system where intelligence is embedded at the sensory front-end is also called a smart sensor. Previous work on designing ultra low-power machine learners for “smart” sensors have shown the benefit of using analog processing and the extreme learning machine (ELM) algorithm. However, the major bottleneck in speed and energy efficiency of those systems has been the conversion of the analog data to the digital domain for multiplication with learned weights. This thesis aims to explore the design of low power ADCs for use in embedded ELM implementations. Key parameters of interest during design are area, resolution, energy per conversion and conversion time. First, a 1-bit ADC (current comparator) is designed for application in a novel ELM based conditional branch prediction system designed for pipelined processors. System simulations results are presented and compared with other traditional algorithms used for branch prediction. A 10-bit, 2-step TDC based ADC is proposed for application in image recognition based analog ELM machine learners. The major building blocks are designed and simulation results are presented.||URI:||http://hdl.handle.net/10356/68254||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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