Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/68687
Title: Low power CMOS circuits with approximate computer arithmetic
Authors: Cheng, Suoyu
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2016
Abstract: Low power consumption is the objective of electronic devices. And now, for many portable multimedia devices, the final output is received by human senses. As human senses are not sensitive as machines and allow the output result to be less accurate, some approximate algorithms trading off accuracy are put forward to reduce the power consumption. Usually, low power consumption is achieved by reducing the number of transistors in the CMOS circuit because fewer transistors in a circuit always mean less power consumption. Many 1-bit imprecise adders which have fewer transistors than the 1-bit precise adder will be designed and compared with each other in this dissertation. In addition, some 4-bit adders established by 1-bit precise and approximate adders will also be designed and discussed. Power consumption, propagation delay and the power-delay product (PDP) are three important parameters of the circuit. Besides, error degree is also an important parameter of approximate arithmetic units when making the comparison. The performance of the approximate arithmetic units is influenced by voltage amplitude and frequency, so simulation about the two factors will be done. After that, a new algorithm, S value, which places different weights on different parameters to determine the best unit is proposed. Finally, comparison of these mathematical units is made by PDP and S value respectively.
URI: http://hdl.handle.net/10356/68687
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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