Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/68709
Title: Ultralow power compressor circuits implementation with different logic styles
Authors: Zhang, Yuxiang
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2016
Abstract: Nowadays, with the increasing use of the portable electronic devices, the ultralow power CMOS circuit design becomes a vital issue. Methods and techniques are developed to achieve the low power consumption for digital system successfully. One of the aggressive approaches is to operate transistors of the digital logic circuit in the sub-threshold or near-threshold region, which is proposed to be an effective way to reduce the power consumption in the digital circuit design. In this project, by employing this technique, several kinds of compressor circuits with ultralow power consumption will be designed and analyzed. However, when the circuits are operating in the near-threshold region, it will experience the speed penalty. As a result, the power-delay production (PDP) will be calculated to get the best trade off between the delay and power consumption for the digital circuits. At the first stage, it will focus on the compressor structures and functionality, including 3-2 compressor, 4-2 compressor and 5-2 compressor. These compressor circuits will be designed in three logic styles — the static circuits, the pass transistor circuits and clock-delayed (CD) domino circuits. Subsequently, the circuit blocks in the different logic design styles will be implemented by the optimized circuits of XOR and MUX sub-blocks. At the second stage, different voltage level and frequency level of input signal will be simulated in each compressor circuit, and all the simulation results will be presented and analyzed in these three aspects — propagation delay, power consumption and power-delay production (PDP) to evaluate the performance of the compressors. In the third stage, the comparison of two different kinds of CD domino circuits would be conducted to obtain the most power-delay efficient circuit architecture.
URI: http://hdl.handle.net/10356/68709
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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