Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/68837
Title: 16-bit low power multiplier design
Authors: Liew Tien Hong
Keywords: DRNTU::Engineering
Issue Date: 2016
Abstract: Binary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In order to minimize delay and power dissipation, Wallace Tree Algorithm (WTA) has been proposed to perform the partial product additions. For further improvement, Carry Lookahead Adder has been proposed for the final addition of the partial product in the final level.
URI: http://hdl.handle.net/10356/68837
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
Final_Report.docx.pdf
  Restricted Access
1.14 MBAdobe PDFView/Open
Appendix A_B_D_E.docx
  Restricted Access
56.09 kBMicrosoft WordView/Open

Page view(s) 50

294
Updated on Nov 26, 2020

Download(s) 50

21
Updated on Nov 26, 2020

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.