Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/68837
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dc.contributor.authorLiew Tien Hong-
dc.date.accessioned2016-06-09T02:56:41Z-
dc.date.available2016-06-09T02:56:41Z-
dc.date.issued2016-
dc.identifier.urihttp://hdl.handle.net/10356/68837-
dc.description.abstractBinary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In order to minimize delay and power dissipation, Wallace Tree Algorithm (WTA) has been proposed to perform the partial product additions. For further improvement, Carry Lookahead Adder has been proposed for the final addition of the partial product in the final level.en_US
dc.format.extent37 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University-
dc.subjectDRNTU::Engineeringen_US
dc.title16-bit low power multiplier designen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorGwee Bah Hweeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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