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|Title:||Novel high-k dielectrics for nanoelectronics||Authors:||Chong, Vanessa Meng Meng||Keywords:||DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects
DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Thin films
|Issue Date:||2016||Source:||Chong, V. M. M. (2016). Novel high-k dielectrics for nanoelectronics. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||The aggressive downsizing in metal-oxide-semiconductor field effect transistors (MOSFET) has been the driving force for performance progress in microelectronics. In association with device parameters related to MOSFET, SiO2 based oxide has already faced to its limit in further thinning due to excess gate leakage current. However, further scaling in equivalent oxide thickness (EOT) down to 0.5 nm or less requires a gate stack with a high k insulating layer. Till date, an EOT below 0.5 nm has been obtained with a careful deposition of a high-k combined with an optimized heat treatment to suppress the SiOx-based low k interfacial layer growth. In addition to this process optimization, studies have revealed that rare earth oxide can achieve a direct contact of a high-k with Si substrate by forming RE-silicates at the interface, which produce dielectric constants of 8 to 20 pending on the amount of incorporated silicon. Nevertheless, developing an alternative gate material with suitable high dielectric constants for approaching CMOS generations is one of the most challenging problems in the continuous development of electronics. The criteria for these materials are stringent. On top of the basic and absolute requirement for higher permittivity (k)-values, the energy band offsets to silicon, interface and bulk charges and thermal stability, are among the various essential properties that need to satisfy the demands set by MOS production processes. This work features the use of titanium oxide (TiO2) and gadolinium silicate (GdSiO) as passivation layers to suppress the undesirable interfacial layer formation when high-k material is in contact with silicon substrate. In addition, to ensure the uniformity and conformality of these thin films, atomic layer deposition (ALD) is chosen to be the most suitable deposition technique to ensure good controllability of the thickness of these passivation layers. The CeO2/TiO2 showed comparable dielectric constants but severe leakage degradation due to the interfacial layer and silicide formation post-annealing. As for CeO2/GdSiO samples, although the k-value is lower (~13) but the leakage current is improved by 4-5 orders of magnitude as compared to CeO2/TiO2. Furthermore, leakage current conduction mechanism showed that upon annealing, the mechanism switches from Schottky to Poole-Frenkel emission for CeO2/GdSiO samples due to bulk CeO2 being dominant caused by oxidation state change of Ce2+ to Ce3+ which leads to oxygen vacancies.||URI:||https://hdl.handle.net/10356/68931||DOI:||10.32657/10356/68931||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||MSE Theses|
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