Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/69185
Title: Adaptive efficiency optimized power regulator for portable devices
Authors: Wu, Chundong
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Power electronics
Issue Date: 2016
Source: Wu, C. (2016). Adaptive efficiency optimized power regulator for portable devices. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: An adaptive efficiency optimized power regulator that can work at load current ranging from mille-ampere to ampere is developed for portable devices. Based on the proposed efficiency tracking method, the power regulator can adjust its efficiency to the highest as the load current or supply voltage varies. An internal 10-µA, trim-free, low temperature coefficient, supply independent current reference with process compensation feature is proposed to ensure that the system remains stable over PVT variations. Without using high gain amplifier, a 130 ppm/°C temperature coefficient current reference across -40°C to 80°C temperature range is achieved. The proposed circuit can work at supply voltage varying from 2.4V to 3.2 V, with only 30-nA current drift at room temperature. To reduce the line regulation of output voltage and clock, an internal merged structure bandgap voltage reference and a temperature independent current reference (BGVCR) is proposed. The bandgap voltage reference segment of the BGVGR is designed to serve as a reference voltage for the power regulator, while the current reference segment function as a reference current for the clock generator to produce a stable clock. The proposed proportional to absolute temperature (PTAT) current sharing approach proposed in this thesis allows amalgamation of the bandgap voltage and current reference in the same structure without them affecting each other’s performance. PTAT sharing helps to compensate process variation in the proposed circuit, thus doing away with the trimming resistor array. A local feedback loop together with parasitic capacitor is deployed to achieve self-start-up. The gain of the voltage tracking loop for generating the PTAT current is also boosted. The proposed compact BGVCR attained 5 ppm/°C temperature coefficient for bandgap voltage reference and 150 ppm/°C temperature coefficient for the current reference across -40°C to 80°C temperature range at 1.8-V internal supply voltage. Using the proposed methodology, the efficiency of the power regulator can be easily tracked using its input current. An enhanced full range current sensor based on self-bias structure for buck regulator is proposed in this thesis to sense the input current of the power regulator. The proposed full range current sensor can sense current from both the high side and low side switches of the power regulator within the same switching cycle. It has higher than 95% sensing accuracy while consuming less than 1% of the total input power. The current sensor is implemented in the power regulator with less than 1% area of the power transistor array. The dead-time of the power regulator must be carefully controlled to achieve best efficiency. Instead of using high gain amplifier for body diode conduction sensing, or zero voltage detecting, a sensor-less adaptive dead-time control driver utilizing predictive idea for dead-time control is proposed. Unlike the conventional predictive method that requires self-adjusting or tuning during testing, a threshold voltage is used as the predictive information for dead-time control. The delay in body-diode conduction sensor or zero voltage detector is totally eliminated from the power regulator. Not only the power consumption of the system is greatly reduced, the control accuracy of the dead-time is also enhanced. With the proposed prediction circuit, less than 3-ns body-diode conduction time is obtained, while the switching loss is minimized which helps the power regulator to achieve more than 95% peak efficiency at 450-mA load with 2.4-V supply voltage. Lastly, a complete power regulator system that includes all the building blocks described above are fabricated in 0.18-μm CMOS process, occupying a silicon area of 2 mm x 2 mm. Based on the proposed efficiency optimized method and embedded building blocks, more than 95% peak efficiency and higher than 84% overall efficiency is achieved at 2.4-V supply voltage across 70-mA to 1.1-A load range with 30 mV/A load regulation. When supply voltage is increased to 3.2 V, the efficiency drop on the converter is less than 3% and the line regulation is less than 1%/V.
URI: https://hdl.handle.net/10356/69185
DOI: 10.32657/10356/69185
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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