dc.contributor.authorXiao, Fei
dc.date.accessioned2016-12-07T09:11:10Z
dc.date.accessioned2017-07-23T08:36:47Z
dc.date.available2016-12-07T09:11:10Z
dc.date.available2017-07-23T08:36:47Z
dc.date.issued2016
dc.identifier.urihttp://hdl.handle.net/10356/69246
dc.description.abstractIn recent years, the demand for the battery-powered devices has been increasing rapidly. At the same time, the requirements for the audio power amplifier (APA) also extend to hi-fi quality music playback. In order to achieve high run time per charge for the portable devices, the quiescent power consumption of APA should be made as low as possible. As such, the quiescent power consumption, harmonic distortion and dynamic range become the most significant performance parameters in the design of high-performance headphone amplifiers. Compared to the class-D amplifier, class AB amplifier has the key advantages of high PSRR, low THD+N, no switching noise and no electro-magnetic interference. In this thesis, a low-quiescent class-AB headphone driver, which is powered by dual supplies of ±1V, is presented and analyzed. Due to the small resistive load of APA, the mismatch-induced quiescent current caused by the input-referred offset voltage becomes a significant effect on the quiescent power consumption. It is evident that the mismatch-induced quiescent current of APA will be substantially increased with the increase of amplifier offset. A new balanced offset compensation current approach is presented. Through the aid of digitally-assisted calibration design, the input-referred offset can be substantially reduced while avoiding the unnecessary increase of quiescent power. Since the compensation current is injected into the low impedance nodes of the front-end gain stage, there is no significant degradation in terms of DC gain and power supply rejection ratio (PSRR) of the amplifier. This has demonstrated the robustness of calibration circuit. An improved compensation technique called NMCFNR2, which is the Type-II implementation of nested Miller compensation with feedforward and nulling resistor (NMCFNR) amplifier, is proposed. It offers the technical advantages of simplicity as well as low-quiescent operation. Besides, the modified frequency compensation permits the APA to drive the worst-case load of 16Ω//2nF whilst sustaining good stability and offering good and balanced performance metrics. Together with the channel-length modulation (CLM) reduced class-AB bias generation circuit dedicated to the push-pull output stage, the auto-calibrated APA will reduce the input-referred offset of amplifier down to about 85µV while the total quiescent power is only 0.4mW and the GBW is of about 1.78 MHz. The APA can deliver a peak power of 35mW (1.5Vpp swing) to the worse case load of (16Ω//2nF) with -89dB THD+N and 93.5dB SNR. The extensive measurement results have suggested that the proposed amplifier has achieved the best Figure-of-Merit FOM1= (Peak load power/Quiescent power) and the best FOM2= [Peak load power/Quiescent power*(THD+N)%] when compared with other representative state-of-the-art works.en_US
dc.format.extent107 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleA CMOS power amplifier in nanometer technology for portable applicationsen_US
dc.typeThesis
dc.contributor.researchCentre for Integrated Circuits and Systemsen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorChan Pak Kwongen_US
dc.description.degreeMASTER OF ENGINEERING (EEE)en_US
dc.identifier.doihttps://doi.org/10.32657/10356/69246


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