Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/69329
Title: Design of low dropout voltage regulator (LDO)
Authors: Cheng, Yilin
Keywords: DRNTU::Engineering
Issue Date: 2016
Abstract: With the growth of the portable, battery –powered mobile systems laptops and other portable electronic devices, the need for efficient voltage regulation to prolong the battery life is very important , so the small size and clean supply voltage are more important for the present and future. In many on-chip systems, low dropout regulators (LDO) are used to provide clean power supply for noise –sensitive building blocks. A fully-integrated low dropout regulator has fast transient response and full spectrum power supply rejection. LDO regulator often used to provide low voltage, low noise and accurate output voltage. This project is to introduce a way to improve the stability of LDO, transient response and good line regulation as well as PSRR. With 10mA full load current and power supply is 1.2V, regulated a output voltage that is 1V with output load is 100pF. Using Cadence ADE Environment to get the simulation results, this is based on 0.18µm CMOS process technology
URI: http://hdl.handle.net/10356/69329
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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