Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/69465
Title: Gate-all-around vertical silicon nanowire (GAA-VSiNW) fets : junction and threshold voltage engineering for optimum performance and scalability
Authors: Lu, Weijie
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2017
Source: Lu, W. (2017). Gate-all-around vertical silicon nanowire (GAA-VSiNW) fets : junction and threshold voltage engineering for optimum performance and scalability. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Gate-All-Around (GAA) Silicon nanowire (SiNW) is a structure with virtually “infinite” number of gates in close vicinity to the channel to provide the best gate-to-channel electrostatic control, and therefore drastically reduces the parasitic short channel effects leading to lower power dissipation when the transistor is turned off. Generally, GAA-SiNW devices are demonstrated in either the lateral or vertical direction. With the limited estate area per wafer, GAA vertical SiNWs (GAA-VSiNWs) are preferred to fully utilize the advantages of the nanowire infrastructure while maximizing the number of transistors per unit area. Due to the one dimensional nature of vertical nanowire, 2 problems arise: (1) Threshold Voltage (VT) of gated nanowire transistors are incorrectly set due to the work function difference between the gate and the undoped channel and (2) high series resistance of the source/drain regions. In this work, to address issue (1), two methods are employed. In the first method, dopants of opposite polarity to the intended device type are used as the gate implant. For example, the gate of nMOS transistor will be implanted with high dosage of p-type dopant and vice versa. From our measurement results, we demonstrate that there is a positive VT shift of ~ 1.5V across different diameters while the short channel effect characteristics remain similar for small diameter GAA-VSiNWs. In the second method, poly-Si gate is replaced with doped fully-silicided (FUSI) gate using nickel silicide (NixSiy) as the gate material. To tackle issue (2), NixSiy Schottky S/D is introduced. However, 2 challenges are associated with NixSiy Schottky S/D: (1) NixSiy intrusion into the silicon nanowire channel during silicidation and (2) the existence of a Schottky barrier which leads to increased contact resistance. By using a two-step rapid thermal annealing (RTA) silicidation methodology, NixSiy intrusion into nanowire can be controlled. VSiNW diodes and Transmission Electron Microscopy (TEM) imaging were used to characterize intrusion lengths into VSiNWs. A low temperature RTA was first used to control the intrusion length and subsequently, a higher temperature RTA was used, after removal of un-reacted Ni, to form the desired nickel silicide phase. From our results, the two-step RTA silicidation showed a 5 times reduction in silicide intrusion length compared to one-step RTA silicidation. At the same time, the two-step RTA silicidation method demonstrated 2 orders in magnitude of reduction in Ireverse, ~14% reduction in ideality factor (from 2.25 to 1.75) and ~28% reduction in effective electron Schottky Barrier Height (SBH) (from 0.7eV to 0.51eV). Dopant Segregated Schottky (DSS) contact was employed to reduce the SBH and in turn, improve the S/D contact resistance. Through the use of silicidation induced dopant segregation (SIDS) method, boron or phosphorus atoms were implanted into the S/D regions before the occurrence of silicidation to segregate the dopants at the NixSiy/Si interface. Using two-step RTA silicidation as standard throughout the experiments, DSSB-VSiNW diodes higher Iforward and lower Ireverse than SB-VSiNW diodes. In addition, DSSB-VSiNW diodes showed ideality factor close to unity (a 61% reduction from 2.25 to 1.15) and ~10% reduction in effective electron SBH (from 0.5eV to 0.45eV). Moreover, the fabricated DSS-VSiNW MOSFETs demonstrated excellent electrical characteristics with an increase of 8% to 29% in drive currents over the SB-VSiNW MOSFETs. From our low temperature measurements, DSS-VSiNW MOSFETs showed ~ 50% reduction in SBH as compared to SB-VSiNW MOSFETs. In addition, DSS-VSiNW MOSFETs demonstrated lower Drain-Induced Barrier Lowering (DIBL) and Sub-threshold swing (SS) short channel effect characteristics over SB-VSiNW MOSFETs.
URI: http://hdl.handle.net/10356/69465
DOI: 10.32657/10356/69465
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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