Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/69500
Title: A PVT-tolerant relaxation oscillator in 65nm CMOS
Authors: Cimbili Bharath Kumar
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2017
Abstract: One of the major problems with integrated oscillators is that of stability against the process, supply and temperature variations. The proposed circuit architecture presents a fully-integrated CMOS relaxation oscillator (ROSC) using a process-voltage-temperature (PVT) insensitive current reference generator. The oscillator circuit is based on a conventional ROSC architecture which includes a PVT insensitive current and a voltage reference circuit, two comparators, two capacitors and an output logic circuit which consists of a SR latch and a frequency divider. The oscillator is designed to generate a clock frequency of 64.4kHz in 65nm CMOS technology. The Monte-Carlo simulation results have shown that the ROSC is able to achieve 3.66% in the process sensitivity (σ/μ). The output frequency variation is 1.71% over the temperature range from ‒20oC to 100oC and 0.73% over the supply variation from 1.2V to 2V. The power consumption of ROSC is 4.32μW at 1.2V supply. It has displayed better figure-of merit (FOM) against PVT variations with respect to other reported prior-art works.
URI: http://hdl.handle.net/10356/69500
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
CimbiliBharathKumar16.pdf
  Restricted Access
1.42 MBAdobe PDFView/Open

Page view(s) 5

206
checked on Sep 23, 2020

Download(s) 5

32
checked on Sep 23, 2020

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.