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|Title:||Improving the productivity of high-level synthesis by advancing reuseability and verifiability||Authors:||Yang, Liwei||Keywords:||DRNTU::Engineering::Computer science and engineering||Issue Date:||2017||Source:||Yang, L. (2017). Improving the productivity of high-level synthesis by advancing reuseability and verifiability. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||As the complexity of applications continues to grow to meet user demands, the complexity of hardware platforms continues to grow correspondingly. Thus, the hardware design flow is a critical methodology to handle continued growth in design complexity. Whether targeting application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), hardware design starts with models and algorithmic specifications in high level languages (HLLs). Following algorithmic specifications, designers perform architectural specification including hardware/software (HW/SW) partitioning. Next, the hardware design is specified in register-transfer level (RTL) description using hardware description languages (HDL) such as Verilog and VHDL. Computer-aided design (CAD) tools then verify functionality and synthesize the RTL into a netlist of circuits, which is further placed and routed into physical design for the implementation. As the size (transistor counts) of integrated circuits (ICs) continuously increase, the productivity of the hardware design flow is a major challenge. The productivity of designing in manual RTL has been growing more slowly than the size and complexity of the designs, emphasizing the need for enhancements in the design flow. High level synthesis (HLS) is an attractive strategy for accelerating the design entry phase by automating transformation of high-level, untimed- or partially-timed specifications to low-level cycle-accurate RTL specifications. HLS improves productivity via both acceleration of design entry through concise HLL descriptions, and software-based behavioral testing. However, despite the significant productivity improvements through HLS, overall design flow productivity still has major challenges. Research in improving design flow productivity include performance monitoring/prediction to identify performance bottlenecks, HW/SW co-design, integration of reusable components, and verification. In an HLS-based hardware design flow, two particular portions have become particular bottlenecks: integration with reusable intellectual property (IP) components, and verification and debugging. In modern designs, IPs constitute about 70% of the overall SoC design which contributes to both productivity gain and quality of results (QoR). Manual RTL design requires significant effort to integrate IPs, perform architectural exploration, and implement communication protocols. Although HLS accelerates design entry for important components, the task of integrating the HLS-generated hardware with other IPs remains significant. Verification and debugging are also critical to HLS-based design flows. Verification consists both of verifying source input and HLS tool correctness. Even in RTL design flows, functional verification consumes over 50% of overall design flow time, but HLS-based design verification is especially challenging. HLS-produced RTL is not human-readable, and thus debugging is particularly time-consuming and cumbersome, back-tracing through hundreds of signals and simulation cycles. Furthermore, verification of the HLS tools is critical; designers must be confident that they can apply any combination of optimizations arbitrarily without concern for whether the tool will produce a functionally correct output. However, HLS tools are different from typical large-scale software; we must verify that the HLS tool output is always functionally correct RTL, not just that the HLS tool runs to completion without error. Therefore, the verification process of the functional correctness of HLS tools has also become a bottleneck that defers the enhancement of QoR, thus preventing HLS from achieving further improved productivity. In this thesis, we present solutions to address the productivity in HLS-based design flows by effectively integrating reusable IPs, and facilitating the verification and debug process both for HLS-produced designs and the HLS tools. Particularly, we present behavioral-level IP integration in HLS that integrates various IP cores with support for internal and external instantiation, variable- and fixed-latency IPs, and both shared and parallel instantiations. In addition, we present an automated framework to facilitate source-level debugging and verification for HLS-produced designs with cross-layer verification and automated discrepancy detection and analysis. Furthermore, we demonstrate how the debugging and verification framework can also be used to debug and verify the HLS tool itself. Together, this thesis demonstrates critical techniques for addressing productivity in HLS-based design flows to improve the ability to use HLS for large and complex designs.||URI:||http://hdl.handle.net/10356/69552||DOI:||10.32657/10356/69552||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||SCSE Theses|
Updated on Oct 15, 2021
Updated on Oct 15, 2021
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