Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/70201
Title: Low power SAR ADC designs for sensing applications
Authors: Yang, Yongkui
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2017
Source: Yang, Y. (2017). Low power SAR ADC designs for sensing applications. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: In sensing systems, ADCs are widely used in sensor interface circuits to convert analog signals to digital signals. Many of the sensing systems require ultra-low power consumption because of their limited power budget. Therefore, the design of ultra-low power ADC that meets the intended performance is a key design challenge for low power sensing applications, such as in healthcare monitoring (e.g., ECG, EEG, neural signal, etc.) and environment monitoring. Besides, a moderate sampling frequency and resolution can meet the requirement of these sensing applications. Compared to Flash ADC, Pipelined ADC and Delta-Sigma ADC, SAR ADC provides a good compromise among energy efficiency, sampling frequency and conversion accuracy for these sensing applications. In this thesis, SAR ADC is chosen as the main architecture to develop low power SAR ADC and four different designs of SAR ADC are proposed. The first version SAR ADC consists mainly of clock boosting circuit, a subtraction and an addition capacitor array, a time-domain comparator, switching logic, output latches, level shifters and some buffers. To achieve ultra-low power, the proposed ADC operates at 0.5 V, deploying a single-ended structure and top plate sampling technique. In order to improve the linearity of the sampling circuit at ultra-low supply voltage, clock boosting circuit with gate signal swinging from 0 to 2VDD is proposed. A non-binary redundant algorithm is applied to correct the inevitable decision errors in the first few conversion steps. From the chip measurement results, it consumes only 16-nW of power and achieves a SNDR of 50.4 dB, which is equivalent to an 8.08 ENOB, with 1 kS/s sampling rate at 0.5-V supply voltage. The second version SAR ADC was designed to optimize on power efficiency, for sparse signals such as the neural spike. Sparse signals have slow varying or flat characteristic across most of the duty cycle, such that the MSBs are the same if variation between two consecutive samples is small. A novel ADC deploying M-bit ADC, N-bit DAC to realize (M+N-3) bits ADC while reducing the power consumption and area is designed. The adaptive sampling scheme has also been adopted to allow selection of either a higher or lower sampling rate in event of sharp and gradual transitions, respectively. Adaptive sampling not only ensures no overflow of input signal to the M-bit ADC but can further reduce the power consumption. This 8-bit SAR ADC consists mainly of a slope detector, 6-bit ADC capacitor array, 5-bit DAC capacitor array, switching logic, dynamic comparator, latches and 8-bit full adder. The measurement results show that it can realize a SNDR of 45.7 dB, which is equivalent to a 7.3 ENOB, with 125 kS/s sampling rate at 1-V supply voltage. When the input signals are neural spikes, the total power consumption of the proposed ADC (at 2 kHz and 20 kHz sampling rates) is able to save about 88% power compared to the conventional ADC (operating at 20 kHz sampling rate). The third version SAR ADC was designed to optimize on power efficiency in terms of system. A reference-voltage regulator-free SAR ADC with self-timed pre-charging for wireless-powered implantable medical devices was designed. Assisted by a self-timed pre-charging technique, the proposed SAR ADC eliminates the power-hungry reference-voltage regulator and the area-consuming decoupling capacitor while maintaining insensitivity to the supply voltage fluctuation. Furthermore, with internally generated sampling clock and asynchronous SAR logics, this SAR ADC can operate at a fully asynchronous mode without any external clock source. Fabricated in the 0.18-µm CMOS technology, the proposed SAR ADC achieves a SNDR of 53.32 dB at 0.8 V with 50 mVpp supply voltage fluctuation, while consuming a total power of 2.72 µW at 300 kS/s sampling rate. The total FOM is 23.9 fJ/conversion-step and the total area occupied is 0.105 mm2. The fourth design is a wide input 12-bit SAR ADC with low power and fast convergence digital background calibration. This SAR ADC is able to convert input signal with a range of 0~4.8 V, operating at 1.2-V supply. By omitting the calibration of 3 LSBs’ weights, the number of multipliers or product is reduced to lower the power consumption. Besides, in order to accelerate the convergence of digital background calibration, 10 LSB offset is injected to the first 10000 samples, followed by 15 LSB offset. The ADC is designed and simulated with a 65 nm CMOS technology, and the digital background is implemented in Matlab. With background calibration, the SNDR of the ADC is improved from 59.6 dB to 65.3 dB, operating at 500 kS/s. and power consumption is 8.39 µW.
URI: http://hdl.handle.net/10356/70201
DOI: 10.32657/10356/70201
Schools: School of Electrical and Electronic Engineering 
Research Centres: Centre for Integrated Circuits and Systems 
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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