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|Title:||Low power clock generators with digital calibration for sustainable building applications||Authors:||Wang, Jiacheng||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Semiconductors||Issue Date:||2017||Publisher:||Nanyang Technological University||Source:||Wang, J. (2017). Low power clock generators with digital calibration for sustainable building applications. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||The growth of human population on Earth has increased the awareness on the need for energy saving. The concept of smart building and life are proposed to connect all household appliances up to clouds to allow users to control these appliances with energy distribution in a smarter manner. With the expansion of mobile device usage and internet cloud applications, we are already moving to the big-data age. At the same time, the rapid developing digital signal processing technique requires the stable clock frequency due to different building environments, such as wide temperature range, variable supply voltage, sunshine time, humidity and so on. This thesis proposes two relaxation oscillator designs and an all-digital phase locked-loop (ADPLL) design as stable clock frequency generators for the sustainable building applications. The first proposed design presents a novel on-chip RC relaxation oscillator with split-capacitor integrator compensation loop technique to achieve a stable output frequency with environment temperature and supply voltage variations. It can provide a stable frequency signal at 13.5 MHz. Measurements results show that the output frequency has ±0.5% and ±0.5%/V variation with temperature range of −30◦C to 120◦C and power supply range of 1.5 − 2.1 V. Moreover, the power consumption of the design yields only 48.8 µW. The second design is also a relaxation oscillator with digital compensation technique to achieve a stable output frequency with environment temperature and supply voltage variations. The digital compensation scheme can avoid the power hungry analog op-amp integrator feedback loop. The digital method not only save more power in the long run, but is easier when comes to CMOS process scaling. Furthermore, an on-chip reference pulse generator is adopted for the compensation. The digital feedback loop tunes loop delay to adjust the output frequency. The test chips were fabricated in a 0.18- µm standard CMOS process. Effects of this digital compensation method has been verified to maintain frequency stability of the relaxation oscillator. The output frequency is stable at 12.77 MHz at 0.9-V power supply voltage. Measurement results showed that the output frequency has only 31ppm/◦C variation with temperature range of -30 to 120◦C after compensation. The frequency variation over the supply voltage is ±0.5%/V. Compared to other state-of-the-art designs, our design achieves better figure of merit (FoM) and has the smallest temperature coefficient. The total power consumption is 56.2 µW when all circuits are enabled. For long term operation, the power consumption can be scaled to only 12.8 µW in the main oscillator. After introducing the two relaxation oscillators, an all-digital PLL is implemented for digital processing clock signal. In order to reduce power consumption, the proposed ADPLL uses only a flip-flop as the phase detector. The injection locked technique is implemented in this design for jitter performance improvement. The measurement results show that the ADPLL can approach 101 dBc/Hz at 100 kHz offset frequency. This design is taped-out in GLOBALFOUDRIES 40-nm CMOS process, which only consume about 1.2 mW at 1-GHz output frequency. In future work, it is going to integrate the on-chip relaxation oscillator and digital PLL together to create an entire on-chip clock generation and distribution system.||URI:||http://hdl.handle.net/10356/70695||DOI:||10.32657/10356/70695||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||IGS Theses|
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Updated on Nov 24, 2020
Updated on Nov 24, 2020
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