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|Title:||Design of asynchronous-logic for power analysis attack countermeasure||Authors:||Lim, James||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2017||Abstract:||Cryptography ensures the security of cipher by performing mathematical functions and computations to transform the plaintext. Advanced Encryption Standard (AES) is currently the most secure symmetric cryptographic algorithm. AES algorithm employs high degree of confusion and diffusion which make it robust against brute-force attack, linear cryptanalysis, and differential cryptanalysis which successfully thwarted its predecessor Data Encryption Standard (DES) cryptographic algorithm. Despite its security, AES-embedded cryptographic devices such as smart cards, are still vulnerable due to Physical Leakage Information (PLI) such as processing timing, electromagnetic emission, and power dissipation leaked to their environment, posing as side-channel. Side-channel analysis (SCA) attack is hard to be controlled as they can be performed with inexpensive monitoring equipment in a relatively short time. Electromagnetic (EM) emission analysis attack is circumvented by decreasing EM emission through current consumption minimization or EM-blocking mechanism such as Faraday cage. Timing analysis attack and Simple Power Analysis (SPA) attack could be prevented by software countermeasures such as randomization and blinding techniques. However, in terms of Differential Power Analysis (DPA) attack, several countermeasures are still extensively researched as this attacks exploits statistical properties of large samples of power dissipation profiles. In this thesis, a design of an asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) dual-rail 32-bit AES Substitution Box (S-Box) is proposed to countermeasure DPA attack. There are three novel features in the proposed S-Box. First, the proposed S-Box operates in async QDI protocol with dual-rail data encoding to minimize power difference for different signal output transitions on both true-value and false-value wires. Second, the proposed S-Box embodies the power-balanced async WeakConditioned Half-Buffer (WCHB) cell approach to realize same number of consecutive output transitions, hence equalizing the power dissipation. Third, the proposed S-Box embodies our novel-designed library cells realize similar capacitive load across different input combinations, hence hiding the dynamic power dissipation. The result concluded that the proposed architecture successfully increased the DPA attack threshold without performance degradation.||URI:||http://hdl.handle.net/10356/70730||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
Updated on May 9, 2021
Updated on May 9, 2021
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