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|Title:||Ultra-low voltage SRAM design||Authors:||Zhou, Jay Yun Jie||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2017||Abstract:||Static Random Access Memory or SRAM, is the most common embedded memory option for Integrated Circuits. With the scaling of supply voltage to close to sub threshold regions, it must still remain operable such that they can still work in ultra-low power battery operated systems. However, the basic operations of a SRAM such as read and write are hugely affected as the supply voltage scales down. This paper aim to present the basics and fundamentals of SRAM such as its operations and performance parameters. Two existing conventional SRAM cell topologies are chosen, namely the 6T SRAM and 8T SRAM cell topology. The performance parameters for these two topologies are simulated and compared with respect to different supply voltages. A 1kb SRAM is also designed using the two existing SRAM cell topologies to learn how the SRAM array operates. All the drawings and simulations are done using electronic design automation tools such as Cadence Virtuoso and STM 65nm CMOS process technology library cells are used for all the simulations.||URI:||http://hdl.handle.net/10356/70808||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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