Vibration testing and structural analysis of chip scale atomic clock

Abstract

This project is a study done to evaluate the clocking performance of a Chip Scale Atomic Clock (CSAC) under Static and Vibrational situations. 3 main tests were carried out on the CSAC- Static Test, Dynamic Test and Simulation.

From the Static Tests, it was found that the CSAC keeps time at a consistent rate, regardless of orientation. In the Dynamic Tests, the CSAC gave the best performance in the Z axis. For the Simulation Tests, the CSAC was found to have the highest stresses, displacements and acceleration forces in the Z direction. In addition, it had 5 resonant frequencies modes that fell within the operating range of 10 to 2000 Hz.

From this study, it has been determined that more research is required for the Dynamic and Simulation Tests in order to have a better understanding of the clocking performance and structural stresses the CSAC experiences during vibration.

The Dynamic Tests can be redone with a new Mount to fasten the CSAC onto. This can be followed up with new tests to determine what kind of Dampers can be added to the assembly to help minimise the vibrations experienced by the CSAC.

For Simulation, a more powerful software can be used to redo the simulations and produce more accurate results. In addition, new computer models of the CSAC and its new mount can be created and experimented with, so as to determine the modifications required to move the resonant frequencies out of the operating frequency range.