Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/71597
Full metadata record
DC FieldValueLanguage
dc.contributor.authorHu, Tengzhou-
dc.date.accessioned2017-05-17T09:17:04Z-
dc.date.available2017-05-17T09:17:04Z-
dc.date.issued2017-
dc.identifier.urihttp://hdl.handle.net/10356/71597-
dc.description.abstractIn the course of teaching undergraduates the basic concept of digital electronics, the faculty imparts the knowledge and skill to analyze and derive the function and output of electronic components. Evaluation is an essential part of learning. Thus, it is crucial for the faculty to continue designing questions for the students to practice. Conventionally, a question designer takes almost half a day to design 5 – 6 questions such that each question’s difficulty is moderated to the undergraduates’ level, along with corresponding solutions. This project aims to deliver a graphical user interface that can procedurally generate questions on logic circuits for the undergraduates to practice, and validate their inputs. For the scope of Technology-Enhanced Learning of Logic Circuits (A), the program aims to deliver cascading logic gate questions and multiplexor questions. The program developed is able to generate questions of logic circuits consisting of random logic gates up to three levels as well as consisting of multiplexor and logic gates. The randomly generated circuits are displayed graphically for the users to practice solving logic circuit problems. The program also produces the solutions for the generated circuits and takes in the users’ input for validation. This report documents the design, development, implementation and testing of the program.en_US
dc.format.extent47 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University-
dc.subjectDRNTU::Engineering::Computer science and engineering::Software::Software engineeringen_US
dc.subjectDRNTU::Science::Mathematics::Discrete mathematics::Algorithmsen_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Information systems::Information interfaces and presentationen_US
dc.titleTechnology-enhanced learning (TEL) of logic circuits (A)en_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorJong Ching Chuenen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
item.fulltextWith Fulltext-
item.grantfulltextrestricted-
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
Files in This Item:
File Description SizeFormat 
fyp report.pdf
  Restricted Access
2.08 MBAdobe PDFView/Open

Page view(s)

148
Updated on Jun 16, 2021

Download(s)

13
Updated on Jun 16, 2021

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.