Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/71830
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dc.contributor.authorLin, Esmond Chengyuan
dc.date.accessioned2017-05-19T05:30:30Z
dc.date.available2017-05-19T05:30:30Z
dc.date.issued2017
dc.identifier.urihttp://hdl.handle.net/10356/71830
dc.description.abstractThis report presents a simulation model design of a 10-bits pipelined ADC with background calibration. The proposed architecture includes a 3-bit ADC, five 1.5-bits ADC and a 2-bit ADC in a cascade. Some non-ideal errors and offsets are introduced in the pipelined ADC during simulation to model the pipelined ADC in reality. The background calibration is done using split ADC method by comparing each stages output of the pipelined ADC with a more accurate output source. The output source is simulated using a more accurate ADCs with lower sampling rate compared to the non-ideal ADC. A calibration algorithm is developed to estimate both extra gain and compensating offset value that should be added to the gain parameter and removed from the offset parameter respectively in each stage of the non-ideal pipelined ADC. The result of the simulation shows that the output waveform of the non-ideal pipelined ADC would gradually converge to the input signal over time with small quantization errors. However, the calibration method is used for correcting linear gain errors in pipelined ADCs. It may not be able to keep up with the error correction if the gain error is nonlinear. More improvement in the calibration method can be done in the future.en_US
dc.format.extent64 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleHigh speed ADCen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorChang, Joseph Sylvesteren_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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