Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/72073
Title: Synaptic plasticity in VLSI : a floating-gate approach
Authors: Gopalakrishnan, Roshan
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2017
Source: Gopalakrishnan, R. (2017). Synaptic plasticity in VLSI : a floating-gate approach. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: One of the major areas of research by neurobiologists is long term synaptic modification or plasticity of synapses. Synapses are the interconnections between neurons. Each synapse is associated with a weight quantity, which determines the amplitude of output excitatory postsynaptic current (EPSC) pulse from the respective synapse to the interconnected neuron. Neurons on the other hand are the basic computational unit. It integrates all the incoming current pulses from different synapses and fires a spike, if the integration reaches a threshold. Neurons and synapses are the major units of a biological neural network that are typically included in computational models; however, recently there has been an increasing focus on studying the role of astrocytes [1, 2] and may be a part of future large scale models. It is generally believed that the ability to learn and execute difficult tasks in human brain is mediated by synapses. Likewise in artificial spiking neural networks (SNNs), synapses play a major role in the ability to carry out signal processing, classification, computations etc. Basically synapses play a fundamental role in learning through activity dependent modification of their efficacies. The mathematical model under which synapses modify their weights are termed as synaptic plasticity rule. Recently a learning rule known as spike timing dependent plasticity (STDP) that modifies weights based on the timing of presynaptic and postsynaptic spikes become very popular. The most commonly used rule posits weight change based on time difference between one presynaptic spike and one postsynaptic spike and is hence termed doublet STDP (D-STDP). Potentiation occurs when a postsynaptic spike succeeds a presynaptic spike; otherwise depression happens. However, D-STDP could not reproduce results of many biological experiments; a triplet STDP (T-STDP) that considers triplets of spikes as the fundamental unit has been proposed recently to explain these observations. Computationally T-STDP has advantages like replicating rate based plasticity experiments and detecting third order input correlations. As these rules are being proposed by neurobiologists, we as engineers try to implement them in silicon in order to employ them in complex real world applications. We first propose a method to robustly perform doublet STDP rule in a single floating-gate (FG) transistor synapse. The experimental STDP plot of a FG synapse (change in weight against Δt = tpost - tpre) from previous study shows a depression instead of potentiation at some range of positive values of Δt. To ameliorate this STDP graph of a FG synapse, a minimum hardware overhead solution is proposed. The measurement results from a FG synapse fabricated in AMS 0.35 m CMOS process design are presented to justify the claim. Next, we propose a modification to the basic FG synapse to implement a more sophisticated and bio-realistic rule - triplet STDP (T-STDP). Compared to the previous work, here we propose a method to localize the effect of potentiation and depression on a FG synapse. The spike triplet affects the setting of drain voltage–we present a single pulse and a double pulse drain voltage method to obtain the desired dependence of weight on spike timing. We present a mathematical procedure to calculate the parameters of the drain voltage pulse to obtain results matched to the original theoretical T-STDP rule. We also show measurement results from a FG synapse fabricated in TSMC 0.35 um CMOS process in comparison with the biological experimental observations for (1) original doublet protocol, (2) two protocols of spike triplets, (3) frequency effects of pairing protocol, (4) quadruplet experiments and (5) replication of BCM rule. Possible VLSI implementation of drain voltage waveform generator circuits are also presented with simulation results. Finally, we showcase the computational advantages of T-STDP model apart from the experimental advantages compared to D-STDP model i.e. detecting third order input correlations and faster convergence of synaptic weights. A classic STDP experiment is chosen and implemented using both D-STDP model and T-STDP model in MATLAB. MATLAB simulations prove the faster convergence of synaptic weights in the case of T-STDP model. To understand the performance of a silicon neural network with integrate and fire neurons and the proposed FG synapses, we have performed SPICE simulations of such a system with a behavioural model of the FG device. The third order correlation model is simulated in SPICE and the results are matched with MATLAB simulations to lay the foundation for future silicon implementations. In future, the work described in this thesis can be extended to make software simulations of larger neural networks with multiple neurons and synapses following the FG based T-STDP learning rules. VLSI implementations of the same may also be fabricated using low-power subthreshold analog techniques. Further, these models may be used to classify realistic spiking image datasets such as the one described in [3].
URI: http://hdl.handle.net/10356/72073
DOI: 10.32657/10356/72073
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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