Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/72588
Title: Controller design for high-frequency switch-mode DC-DC converters
Authors: Rajendra Anojh Kumaran
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2017
Abstract: DC-DC converters are commonly employed to perform the voltage conversions with high power-efficiencies; however, they require off-chip external filters that are bulky and costly in terms of board area. The trend in DC-DC converter design is to realize on-chip/fully-integrated DC-DC converters with small on-chip filters. These DC-DC converters are particularly attractive for low-power portable applications. Reducing the size of the filter is done by increasing the switching-frequency since the output filter size is inversely proportional to the frequency. Since high switching-frequencies (≥10 MHz up to hundreds of MHz) are required, controllers for low-power DC-DC converters are often based on analog circuits rather than digital circuits, primarily due to their low power consumption, although the latter offers various advantages such as programmability, low sensitivity to process and parameter variations, and scalability to lower voltage and advanced CMOS technologies. This Master of Science project pertains to the analysis and design of a low-power digital controller and a multi-phase DC-DC converter topology for high-frequency fully-integrated switch-mode DC-DC converters. The first contribution of this project is the design of a high-frequency digital controller based on the Proportional-Integral-Derivative (PID) control algorithm. The difference equation which performs the compensation in the controller is (hardware) optimized to reduced its complexity while maintaining an equivalent mathematical operation. The optimization reduces the number of multipliers by 6, and adders by 4. Compared to the digital compensator without the hardware optimization, the power dissipation of the hardware optimized digital compensator is reduced by 90% when implemented using CMOS 180 nm. The DC-DC Buck converter is designed to operate at 100 MHz with 3.6 V supply to produce a fixed output of 1.8 V. Simulation results of the DC-DC converter, employing the controller, shows that the critically damped closed loop response is achieved with a settling time of 1us. Additionally, the filter capacitor values are designed such that output ripple is 1% of the output voltage. However, this could be compromised depending on the resolution of the A/D converter and the DPWM. With a 6-bit A/D converter and a 5 bit DPWM, the maximum output ripple at steady state is found to be within 5% of the output voltage. The second contribution of this project is the design of a multi-phase interleaving topology for high-frequency fully-integrated DC-DC converters. The output current ripple is perfectly cancelled by connecting two converters in parallel and controlling the switching stage from duty-cycle signals which are out-of-phase by 180o. Finally, the Inductor of the output filter is modelled using the packaging inductor of MQFP package, utilizing a combination of Bond-wire and Lead inductances. Simulation results ensure a 50% improvement on the peak-to-peak output current ripple, after the 2-phase design and output filter modelling is incorporated in to the analysis.
URI: http://hdl.handle.net/10356/72588
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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