Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/72875
Title: Analysis and design of an adaptive-supply class H audio power amplifier for mobile devices
Authors: Zhang, Xiang
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2017
Source: Zhang, X. (2017). Analysis and design of an adaptive-supply class H audio power amplifier for mobile devices. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: In recent years, the market of consumer electronics has witnessed a growing demand for portable devices with high-fidelity audio playback functionality. For battery-powered devices like smart phones, smart watches and tablets, their form factor as well as weight keep on shrinking to enable the good portability required by the customers. As a result, the board space left for the battery is likely to be further reduced. On the other hand, more functional blocks are expected to be integrated into the system which will deplete the battery even more quickly. Therefore, low quiescent power and high power efficiency have become key performance metrics for audio amplifiers designed for portable applications. Switched mode amplifiers such as class D amplifier have been quite popular in the market of audio amplifiers. Its switching nature minimizes the conduction loss of the output stage and hence high power efficiency is achieved. However, it is generally considered inferior in linearity as compared to its linear amplifier counterparts. More importantly, the switching noise generated at the output stage will cause electromagnetic interference (EMI) problems which may affect the performance of other Radio Frequency (RF) blocks. Besides, its output filter is comprised of huge inductor and capacitor which increases the implementation cost. Therefore, this research project focuses on the development of high linearity, high efficiency linear amplifiers for audio applications. In order to enhance the power efficiency of a typical linear amplifier, e.g. class AB amplifier, emphasis should be drawn on the conduction losses at the output stage. The supply voltage is usually determined based on the requirement of the output voltage swing. However, when the output swing becomes small, there will be substantial amount of voltage drops across the power transistors which ultimately leads to conduction losses. As a straightforward solution, class G amplifier which uses two different supply rails for the output stage is proposed. However, the power efficiency is still low once the higher supply rail is selected. To further optimize the power efficiency, we proposed a novel class H architecture which operates with only single-rail supply. The supply to the output stage is designed to be adaptive to the instant input signal level so that the voltage drop across the power transistor is kept constant. Therefore, compared with other linear amplifier architectures (class B/AB/G), the proposed design features much better overall power efficiency. An existing issue with the above-mentioned adaptive-supply amplifiers is the additional distortions that occur during mode switching. For class G topology when the switching threshold is reached, the supply voltage sees step changes during the low to high transitions. These abrupt changes tend to add distortions to the outputs of the amplifier. Therefore, for conventional adaptive-supply amplifiers, there is a sudden burst in the Total Harmonic Distortion (THD) when the high supply starts operating. In this research, we proposed a common-mode modulation (CMM) scheme to resolve this problem. Instead of changing the system configuration upon the triggering of mode switching, the amplitude information of the input signal is extracted and embedded into the common-mode (CM) voltage of the output. As the CM voltage cancels out at the output stage, this scheme yield a much more smooth transition during mode switching, and no additional distortion is added to the output signal. To validate the proposed amplifier architecture, a prototype of the design was fabricated in the 0.18-µm CMOS process. Measurement results show that the proposed amplifier achieves 80.4% peak power efficiency which is the highest among all linear amplifiers in the literature. In the intermediate output power range it demonstrates more than 25% higher power efficiency as compared to class AB and class G amplifiers. It also achieves a lowest THD+N value of -80.5 dB and no degradation on THD+N performance is observed during mode transition. Thus, the high linearity is preserved for the entire load range. Its quiescent power consumed by the whole system is 3.52 mW which is also significantly lower than the benchmark class H amplifier design due to the reduced circuit complexity
URI: http://hdl.handle.net/10356/72875
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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