Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/73107
Title: Study and analysis of MRAM/RRAM-based circuit design for emerging applications
Authors: Yang, Ziang
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2018
Abstract: In recent years, CMOS-based conventional memory technologies including SRAM, DRAM, and Flash memories have become system performance bottleneck due to the speed gap between memory and logic, where they consume a large portion of power within systems, and not only that, they will soon face technology and economic issues as CMOS scaling approaches the fundamental limit. Emerging Non-Volatile Memory (NVM) technologies such as Magnetic RAM (MRAM) and Resistive RAM (RRAM) are recognized as promising candidatures for next-generation memory systems owing to several appealing properties: non-volatile, high density and scalability, fast speed, universal adaptability and multiple-bit capacity. In addition to be memory storage, NVM also offers many unique applications based on its physical properties. In this dissertation, the author has reviewed two typical NVM technologies, including MRAM and RRAM, and their related applications. The MRAM is thereby selected as a case study to explore security application, i.e., Physical Unclonable Function (PUF) circuit design. A modified MRAM model is established by Verilog-A and the MRAM model, which includes statistical distribution of physical parameters for Monte Carlo simulation that models the process variation of Magnetic Tunnel Junction (MTJ) in MRAM. By utilizing the mismatch variation of MTJ device for Internet of Things (IoT) hardware security application, a MRAM based PUF has been designed. Statistical data are generated using the Cadence Measurement Description Language (MDL) with Spectre simulator to perform mixedlanguage Monte Carlo simulation. A dual-mode MRAM architecture, including MRAM arrays and sense amplifier (SA), has also been studied and explored to implement functions of both memory and PUF. The simulation calculated are based on 65 nm CMOS technology and 45 nm radius MTJ.
URI: http://hdl.handle.net/10356/73107
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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