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Title: Speed up verification with hardware accelerator
Authors: Liu, Yi
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2018
Abstract: The huge and never-stop-growing number of components integrated in System on Chip (SoC) makes the SoC increasingly complex. It also makes the normal ways of verification a bottleneck in the Integrated Circuit (IC) design process due to the cost and time-to-market requirement. The dissertation presents the development of the transaction level communication component to speed up Global Navigation Satellite System (GNSS) boot load simulation based on a co-emulation environment which integrates the simulator and the Mentor Graphics’ emulator—Veloce2. The main task of this work is to build the TBX and get the boot load test passed.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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