Speed up verification with hardware accelerator

Abstract

The huge and never-stop-growing number of components integrated in System on Chip (SoC) makes the SoC increasingly complex. It also makes the normal ways of verification a bottleneck in the Integrated Circuit (IC) design process due to the cost and time-to-market requirement. The dissertation presents the development of the transaction level communication component to speed up Global Navigation Satellite System (GNSS) boot load simulation based on a co-emulation environment which integrates the simulator and the Mentor Graphics’ emulator—Veloce2. The main task of this work is to build the TBX and get the boot load test passed.