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|Title:||Verification of CPU power management unit||Authors:||Varsha Govind Raj||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2018||Abstract:||Modern day high performance CPUs have been extensively designed for 3D gaming, automotive, medical and other applications which are power-hungry and result in high power consumption. Since the devices that host these applications must be sleek and portable, heat and power dissipation must be minimized significantly. Power consumption also contributes significantly towards the battery life of mobile hand held devices. Due to these concerns, designing power efficient high performance CPUs has increasingly become a critical consideration. The crucial tasks in limiting power consumption including clock gating, disabling unused or underused resources are some among the several features that are implemented in a CPU Power Management Unit (CPMU). The CPMU also plays a significant role in booting up the CPU module within the System-on-Chip (SoC). While significant time and effort is contributed in designing an efficient hardware unit like CPMU, functional and performance verifications are equally important. It is crucial to ensure that the hardware block indeed performs the specified functionality and conforms to the design specifications. As the hardware design complexity increases, more robust techniques must be employed to verify it completely. This MSc. project pertains to the investigation of hardware design verification, verification methodologies and specifically, the implementation of these verification methods to verify the CPMU. In this dissertation, coverage driven constrained random verification approach has been investigated and adopted for verifying the CPMU. A robust, configurable and reusable verification environment was developed using System Verilog based Universal Verification Methodology (UVM). The UVM 1.2 release tool has been used in this project. Test scenarios were identified to verify several features and functionalities of the CPMU. Stimuli were accordingly generated and applied to the Design under Test (DUT). The expected output was computed and compared against the DUT’s actual output to detect the design bugs. Functional coverage points were identified and coded. Code and Functional coverage reports were generated to obtain feedback on the quality of the generated stimuli. Based on this feedback, tests were modified/ added to target uncovered design space. Assessment of coverage reports along with regression and bug reports was used to drive verification to closure.||URI:||http://hdl.handle.net/10356/73142||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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