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|Title:||Design of a one-watt level RF power amplifier for smartphones||Authors:||Yu, Jia||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2018||Source:||Yu, J. (2018). Design of a one-watt level RF power amplifier for smartphones. Master's thesis, Nanyang Technological University, Singapore.||Abstract:||Smartphones, embodying wireless data and voice communications means, are increasingly the wireless communications transceiver (phone) of choice. Nevertheless, the primary complaint of smartphone users is the short battery lifespan between charges, and this complaint is exacerbated with the increasing speed and the amount of data communications, particularly with the existing 4G Long Term Evolution (LTE) data and impending 5G data communication protocols. The radio frequency (RF) power amplifier is one of the most critical blocks in the smartphone, in part because it is often the most power-consumptive and power-dissipative block therein. To address the said short battery lifespan, it is imperative that the power dissipation of the RF power amplifier be low and its power-efficiency high. In this MEng program, we identify that the ultra-thin substrate thickness in CMOS processes can drastically degrade the parameters of the transformer, including the parasitic resistances, quality factor, coupling factor, and power-efficiency. The most appropriate substrate thickness option of the GF 65nm CMOS process is selected to improve the thermal dissipation without compromising the performance of the transformer. Our designed CMOS RF power amplifier uses the series-combining transformer to combine the power cells in order to achieve approximately 30dBm maximum output power. To improve the power-efficiency of the series-combing transformer, we analyze and investigate the influence of the non-ideal center tap at the primary winding of the series-combining transformer. We derive an analytical expression and show that how the parasitic resistance between the non-ideal center tap and the real ground, and the process variation degrade the power efficiency of the transformer due to the non-ideal center tap of the transformer. Further, we model the bonding wires of the 32pin QFN (5mm x 5mm) package, including the co-simulations of the CMOS RF power amplifier circuit and 32pin QFN (5mm x 5mm) package. The bonding wire structure is subsequently designed to reduce the power loss at the supply and ground nodes, thereby somewhat improving the power efficiency. We design and monolithically realize a CMOS RF power amplifier prototype that embodies a custom-designed output transformer with ideal center taps at primary windings. The designed RF power amplifier was monolithically realized, achieving 29.3dBm maximum output power and 17.29% PAE; the PAE is somewhat lower than reported designs. We attribute the low PAE to the insufficiently rigorous extraction and modeling of the wide and long metal lines. Improvements to rectify the low PAE are suggested in our future work. For the intended 4G LTE applications, the spectrum emission masks of the 20MHz QPSK and 16QAM LTE signals are fulfilled at the 23dBm output power.||URI:||http://hdl.handle.net/10356/73232||DOI:||10.32657/10356/73232||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Jun 22, 2021
Updated on Jun 22, 2021
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