HetNet enabled RF IC UWB-LNA design

Abstract

This report will discuss the designing of an Ultra-Wide-Band Low Noise Amplifier (UWB-LNA) using 40nm CMOS technology from Taiwan Semiconductor Manufacturing Company Limited (TSMC), with all the individual parameters which needed to be consider met. The aim of this project is to implement current methodologies on to the 40nm CMOS technology to design a UWB-LNA that operates with a bandwidth of 7 GHz, covering the frequencies from 3 GHz to 10 GHz. A basic design of a 6.2 GHz low-noise amplifier will be first discussed in order to grasp the fundamental concepts of designing the low noise amplifier as well as to familiarize the use of Cadence 6 simulation software from Cadence Design Systems, Inc. The design is then further modified with bandwidth extending techniques to achieve the desired response of an UWB-LNA, with a pre-defined specification, referencing to a UWB-LNA of comparable specifications built using the 180nm technology. The proposed design consists of a self-defined transistor core from the TSMC’s 40nm CMOS library, with the inclusion of a Resistor-Capacitor Drain-Gate feedback, coupled with Bridge-Shunt and Series Peaking techniques. The proposed design of the UWB-LNA resulted within the operating band of 2.67 GHz to 10 GHz with a 9 to 10 dB gain, achieved S11 below -10 dB, noise figure of less than 2.25 dB, unconditional stability, P1dB of ~ -5dBm, IIP3 of 15dBm, all drawing a DC power of 15.4 mW.