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Title: Development of micro-strip GaN-on-SiC backside via holes process
Authors: Yu, Zhuoran
Keywords: DRNTU::Engineering
Issue Date: 2018
Abstract: GaN-on-SiC HEMTs have gained remarkable attention due to their potential to revolutionize power and RF electronics as it has highest output power density amongst all solid state semiconductor devices Although much progress in HEMTs has been made, via-holes remain critical routes to improve DC and RF electrical performance for micro-strip circuits. From this project, you can understand how the Via hole was fabricated in the cleanroom by a lot of experiments like Lapping, Dry etching, photolithograph, Ni Plating and so on. My project will mainly concentrate on the processes of SiC lapping and dry etching. The details will be introduced in the following chapters.
Schools: School of Electrical and Electronic Engineering 
Research Centres: Temasek Laboratories @ NTU 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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