Design of a CMOS op-amp with class ab rail-to-rail output stage

Abstract

The universal demand for low power devices led to the downscaling of process technologies. As a result, low supply voltage circuits are made possible. This allows for wider applications in portable, battery-powered devices. As Op-Amps are one of the essential blocks in analog-circuit designs, they need to be continuously made better to match the rapidly advancing electronics industry. However, low supply voltage limits the dynamic range of the Op-Amp. Therefore, there is a need to implement a rail-to-rail output. This means that the output voltage will swing to within millivolts of either supply rail. This is so that every bit of the low supply voltage is utilized. Since the Op-Amps are often used to drive resistive loads, power amplifiers are often integrated. In order to achieve low power consumption, Class AB output stage is frequently used. The designed project consists of a Constant - Gm biasing circuit to ensure that transistors are operating in saturation region. A folded-cascode design is used as the input stage. A Class AB driver stage was also integrated in the input stage, eliminating the need for additional bias source. It makes use of a floating architecture. In general, it is a simple current source that is used to bias the output transistors. The designed project provides an open loop gain of 77.7dB and a phase margin of 70°. The total harmonic distortion is minimized and the quiescent current is about 5% of the maximum output drive. Cadence Custom IC Design Tools (Virtuoso Front to Back Design Environment) was used to design the circuit with AMS 0.18µm CMOS process technology.